forked from OSchip/llvm-project
596 lines
22 KiB
C++
596 lines
22 KiB
C++
//===-- ARMTargetTransformInfo.cpp - ARM specific TTI pass ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements a TargetTransformInfo analysis pass specific to the
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/// ARM target machine. It uses the target's detailed information to provide
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/// more precise answers to certain TTI queries, while letting the target
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/// independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/CostTable.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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#define DEBUG_TYPE "armtti"
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// Declare the pass initialization routine locally as target-specific passes
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// don't have a target-wide initialization entry point, and so we rely on the
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// pass constructor initialization.
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namespace llvm {
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void initializeARMTTIPass(PassRegistry &);
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}
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namespace {
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class ARMTTI final : public ImmutablePass, public TargetTransformInfo {
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const ARMBaseTargetMachine *TM;
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const ARMSubtarget *ST;
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const ARMTargetLowering *TLI;
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/// Estimate the overhead of scalarizing an instruction. Insert and Extract
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/// are set if the result needs to be inserted and/or extracted from vectors.
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unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
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public:
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ARMTTI() : ImmutablePass(ID), TM(nullptr), ST(nullptr), TLI(nullptr) {
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llvm_unreachable("This pass cannot be directly constructed");
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}
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ARMTTI(const ARMBaseTargetMachine *TM)
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: ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
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TLI(TM->getSubtargetImpl()->getTargetLowering()) {
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initializeARMTTIPass(*PassRegistry::getPassRegistry());
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}
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void initializePass() override {
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pushTTIStack(this);
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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TargetTransformInfo::getAnalysisUsage(AU);
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}
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/// Pass identification.
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static char ID;
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/// Provide necessary pointer adjustments for the two base classes.
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void *getAdjustedAnalysisPointer(const void *ID) override {
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if (ID == &TargetTransformInfo::ID)
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return (TargetTransformInfo*)this;
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return this;
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}
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/// \name Scalar TTI Implementations
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/// @{
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using TargetTransformInfo::getIntImmCost;
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unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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unsigned getNumberOfRegisters(bool Vector) const override {
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if (Vector) {
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if (ST->hasNEON())
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return 16;
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return 0;
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}
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if (ST->isThumb1Only())
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return 8;
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return 13;
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}
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unsigned getRegisterBitWidth(bool Vector) const override {
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if (Vector) {
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if (ST->hasNEON())
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return 128;
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return 0;
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}
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return 32;
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}
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unsigned getMaxInterleaveFactor() const override {
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// These are out of order CPUs:
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if (ST->isCortexA15() || ST->isSwift())
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return 2;
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return 1;
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}
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unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
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int Index, Type *SubTp) const override;
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unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
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Type *Src) const override;
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unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
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Type *CondTy) const override;
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unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
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unsigned Index) const override;
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unsigned getAddressComputationCost(Type *Val,
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bool IsComplex) const override;
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unsigned getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, OperandValueKind Op1Info = OK_AnyValue,
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OperandValueKind Op2Info = OK_AnyValue,
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OperandValueProperties Opd1PropInfo = OP_None,
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OperandValueProperties Opd2PropInfo = OP_None) const override;
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unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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unsigned AddressSpace) const override;
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/// @}
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};
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} // end anonymous namespace
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INITIALIZE_AG_PASS(ARMTTI, TargetTransformInfo, "armtti",
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"ARM Target Transform Info", true, true, false)
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char ARMTTI::ID = 0;
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ImmutablePass *
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llvm::createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM) {
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return new ARMTTI(TM);
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}
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unsigned ARMTTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
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assert(Ty->isIntegerTy());
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unsigned Bits = Ty->getPrimitiveSizeInBits();
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if (Bits == 0 || Bits > 32)
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return 4;
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int32_t SImmVal = Imm.getSExtValue();
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uint32_t ZImmVal = Imm.getZExtValue();
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if (!ST->isThumb()) {
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if ((SImmVal >= 0 && SImmVal < 65536) ||
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(ARM_AM::getSOImmVal(ZImmVal) != -1) ||
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(ARM_AM::getSOImmVal(~ZImmVal) != -1))
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return 1;
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return ST->hasV6T2Ops() ? 2 : 3;
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}
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if (ST->isThumb2()) {
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if ((SImmVal >= 0 && SImmVal < 65536) ||
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(ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
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(ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
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return 1;
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return ST->hasV6T2Ops() ? 2 : 3;
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}
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// Thumb1.
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if (SImmVal >= 0 && SImmVal < 256)
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return 1;
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if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
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return 2;
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// Load from constantpool.
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return 3;
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}
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unsigned ARMTTI::getCastInstrCost(unsigned Opcode, Type *Dst,
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Type *Src) const {
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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// Single to/from double precision conversions.
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static const CostTblEntry<MVT::SimpleValueType> NEONFltDblTbl[] = {
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// Vector fptrunc/fpext conversions.
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{ ISD::FP_ROUND, MVT::v2f64, 2 },
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{ ISD::FP_EXTEND, MVT::v2f32, 2 },
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{ ISD::FP_EXTEND, MVT::v4f32, 4 }
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};
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if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
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ISD == ISD::FP_EXTEND)) {
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
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int Idx = CostTableLookup(NEONFltDblTbl, ISD, LT.second);
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if (Idx != -1)
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return LT.first * NEONFltDblTbl[Idx].Cost;
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}
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EVT SrcTy = TLI->getValueType(Src);
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EVT DstTy = TLI->getValueType(Dst);
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if (!SrcTy.isSimple() || !DstTy.isSimple())
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return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
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// Some arithmetic, load and store operations have specific instructions
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// to cast up/down their types automatically at no extra cost.
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// TODO: Get these tables to know at least what the related operations are.
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static const TypeConversionCostTblEntry<MVT::SimpleValueType>
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NEONVectorConversionTbl[] = {
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{ ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
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{ ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
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{ ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
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{ ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
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{ ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
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{ ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
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// The number of vmovl instructions for the extension.
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{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
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{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
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{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
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{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
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{ ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
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{ ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
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{ ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
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{ ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
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{ ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
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{ ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
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// Operations that we legalize using splitting.
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{ ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
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{ ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
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// Vector float <-> i32 conversions.
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
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{ ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
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{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
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{ ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
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{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
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{ ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
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{ ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
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{ ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
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{ ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
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{ ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
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{ ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
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{ ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
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{ ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 },
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{ ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
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{ ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
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// Vector double <-> i32 conversions.
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
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{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
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{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
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{ ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
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{ ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 },
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{ ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
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{ ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 }
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};
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if (SrcTy.isVector() && ST->hasNEON()) {
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int Idx = ConvertCostTableLookup(NEONVectorConversionTbl, ISD,
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DstTy.getSimpleVT(), SrcTy.getSimpleVT());
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if (Idx != -1)
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return NEONVectorConversionTbl[Idx].Cost;
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}
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// Scalar float to integer conversions.
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static const TypeConversionCostTblEntry<MVT::SimpleValueType>
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NEONFloatConversionTbl[] = {
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{ ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
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{ ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
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{ ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
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{ ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 },
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{ ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
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{ ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
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{ ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 },
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{ ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 },
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{ ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
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{ ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
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{ ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 },
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{ ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 },
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{ ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 },
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{ ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 },
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{ ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 },
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{ ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 },
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{ ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 },
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{ ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 },
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{ ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 },
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{ ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 }
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};
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if (SrcTy.isFloatingPoint() && ST->hasNEON()) {
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int Idx = ConvertCostTableLookup(NEONFloatConversionTbl, ISD,
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DstTy.getSimpleVT(), SrcTy.getSimpleVT());
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if (Idx != -1)
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return NEONFloatConversionTbl[Idx].Cost;
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}
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// Scalar integer to float conversions.
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static const TypeConversionCostTblEntry<MVT::SimpleValueType>
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NEONIntegerConversionTbl[] = {
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{ ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 },
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{ ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 },
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{ ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 },
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{ ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 },
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{ ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 },
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{ ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 },
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{ ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 },
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{ ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 },
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{ ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 },
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{ ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 },
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{ ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 },
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{ ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 },
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{ ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 },
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{ ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 },
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{ ISD::SINT_TO_FP, MVT::f64, MVT::i64, 10 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i64, 10 }
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};
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if (SrcTy.isInteger() && ST->hasNEON()) {
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int Idx = ConvertCostTableLookup(NEONIntegerConversionTbl, ISD,
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DstTy.getSimpleVT(), SrcTy.getSimpleVT());
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if (Idx != -1)
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return NEONIntegerConversionTbl[Idx].Cost;
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}
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// Scalar integer conversion costs.
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static const TypeConversionCostTblEntry<MVT::SimpleValueType>
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ARMIntegerConversionTbl[] = {
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// i16 -> i64 requires two dependent operations.
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{ ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 },
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// Truncates on i64 are assumed to be free.
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{ ISD::TRUNCATE, MVT::i32, MVT::i64, 0 },
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{ ISD::TRUNCATE, MVT::i16, MVT::i64, 0 },
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{ ISD::TRUNCATE, MVT::i8, MVT::i64, 0 },
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{ ISD::TRUNCATE, MVT::i1, MVT::i64, 0 }
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};
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if (SrcTy.isInteger()) {
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int Idx = ConvertCostTableLookup(ARMIntegerConversionTbl, ISD,
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DstTy.getSimpleVT(), SrcTy.getSimpleVT());
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if (Idx != -1)
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return ARMIntegerConversionTbl[Idx].Cost;
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}
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return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
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}
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unsigned ARMTTI::getVectorInstrCost(unsigned Opcode, Type *ValTy,
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unsigned Index) const {
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// Penalize inserting into an D-subregister. We end up with a three times
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// lower estimated throughput on swift.
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if (ST->isSwift() &&
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Opcode == Instruction::InsertElement &&
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ValTy->isVectorTy() &&
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ValTy->getScalarSizeInBits() <= 32)
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return 3;
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// Cross-class copies are expensive on many microarchitectures,
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// so assume they are expensive by default.
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if ((Opcode == Instruction::InsertElement ||
|
|
Opcode == Instruction::ExtractElement) &&
|
|
ValTy->getVectorElementType()->isIntegerTy())
|
|
return 3;
|
|
|
|
return TargetTransformInfo::getVectorInstrCost(Opcode, ValTy, Index);
|
|
}
|
|
|
|
unsigned ARMTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
|
|
Type *CondTy) const {
|
|
|
|
int ISD = TLI->InstructionOpcodeToISD(Opcode);
|
|
// On NEON a a vector select gets lowered to vbsl.
|
|
if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
|
|
// Lowering of some vector selects is currently far from perfect.
|
|
static const TypeConversionCostTblEntry<MVT::SimpleValueType>
|
|
NEONVectorSelectTbl[] = {
|
|
{ ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 },
|
|
{ ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 },
|
|
{ ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 },
|
|
{ ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
|
|
{ ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
|
|
{ ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 }
|
|
};
|
|
|
|
EVT SelCondTy = TLI->getValueType(CondTy);
|
|
EVT SelValTy = TLI->getValueType(ValTy);
|
|
if (SelCondTy.isSimple() && SelValTy.isSimple()) {
|
|
int Idx = ConvertCostTableLookup(NEONVectorSelectTbl, ISD,
|
|
SelCondTy.getSimpleVT(),
|
|
SelValTy.getSimpleVT());
|
|
if (Idx != -1)
|
|
return NEONVectorSelectTbl[Idx].Cost;
|
|
}
|
|
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
|
|
return LT.first;
|
|
}
|
|
|
|
return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
|
|
}
|
|
|
|
unsigned ARMTTI::getAddressComputationCost(Type *Ty, bool IsComplex) const {
|
|
// Address computations in vectorized code with non-consecutive addresses will
|
|
// likely result in more instructions compared to scalar code where the
|
|
// computation can more often be merged into the index mode. The resulting
|
|
// extra micro-ops can significantly decrease throughput.
|
|
unsigned NumVectorInstToHideOverhead = 10;
|
|
|
|
if (Ty->isVectorTy() && IsComplex)
|
|
return NumVectorInstToHideOverhead;
|
|
|
|
// In many cases the address computation is not merged into the instruction
|
|
// addressing mode.
|
|
return 1;
|
|
}
|
|
|
|
unsigned ARMTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
|
|
Type *SubTp) const {
|
|
// We only handle costs of reverse and alternate shuffles for now.
|
|
if (Kind != SK_Reverse && Kind != SK_Alternate)
|
|
return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
|
|
|
|
if (Kind == SK_Reverse) {
|
|
static const CostTblEntry<MVT::SimpleValueType> NEONShuffleTbl[] = {
|
|
// Reverse shuffle cost one instruction if we are shuffling within a
|
|
// double word (vrev) or two if we shuffle a quad word (vrev, vext).
|
|
{ISD::VECTOR_SHUFFLE, MVT::v2i32, 1},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
|
|
|
|
{ISD::VECTOR_SHUFFLE, MVT::v4i32, 2},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v8i16, 2},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v16i8, 2}};
|
|
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
|
|
|
|
int Idx = CostTableLookup(NEONShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
|
|
if (Idx == -1)
|
|
return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
|
|
|
|
return LT.first * NEONShuffleTbl[Idx].Cost;
|
|
}
|
|
if (Kind == SK_Alternate) {
|
|
static const CostTblEntry<MVT::SimpleValueType> NEONAltShuffleTbl[] = {
|
|
// Alt shuffle cost table for ARM. Cost is the number of instructions
|
|
// required to create the shuffled vector.
|
|
|
|
{ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v2i32, 1},
|
|
|
|
{ISD::VECTOR_SHUFFLE, MVT::v4i32, 2},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v4i16, 2},
|
|
|
|
{ISD::VECTOR_SHUFFLE, MVT::v8i16, 16},
|
|
|
|
{ISD::VECTOR_SHUFFLE, MVT::v16i8, 32}};
|
|
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
|
|
int Idx =
|
|
CostTableLookup(NEONAltShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
|
|
if (Idx == -1)
|
|
return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
|
|
return LT.first * NEONAltShuffleTbl[Idx].Cost;
|
|
}
|
|
return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
|
|
}
|
|
|
|
unsigned ARMTTI::getArithmeticInstrCost(
|
|
unsigned Opcode, Type *Ty, OperandValueKind Op1Info,
|
|
OperandValueKind Op2Info, OperandValueProperties Opd1PropInfo,
|
|
OperandValueProperties Opd2PropInfo) const {
|
|
|
|
int ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
|
|
|
|
const unsigned FunctionCallDivCost = 20;
|
|
const unsigned ReciprocalDivCost = 10;
|
|
static const CostTblEntry<MVT::SimpleValueType> CostTbl[] = {
|
|
// Division.
|
|
// These costs are somewhat random. Choose a cost of 20 to indicate that
|
|
// vectorizing devision (added function call) is going to be very expensive.
|
|
// Double registers types.
|
|
{ ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
|
|
{ ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost},
|
|
{ ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost},
|
|
{ ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost},
|
|
{ ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost},
|
|
{ ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost},
|
|
{ ISD::SDIV, MVT::v4i16, ReciprocalDivCost},
|
|
{ ISD::UDIV, MVT::v4i16, ReciprocalDivCost},
|
|
{ ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost},
|
|
{ ISD::SDIV, MVT::v8i8, ReciprocalDivCost},
|
|
{ ISD::UDIV, MVT::v8i8, ReciprocalDivCost},
|
|
{ ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost},
|
|
// Quad register types.
|
|
{ ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
|
|
{ ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost},
|
|
{ ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost},
|
|
{ ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost},
|
|
{ ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost},
|
|
{ ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost},
|
|
{ ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
|
|
{ ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost},
|
|
{ ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost},
|
|
{ ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
|
|
{ ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost},
|
|
{ ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
|
|
// Multiplication.
|
|
};
|
|
|
|
int Idx = -1;
|
|
|
|
if (ST->hasNEON())
|
|
Idx = CostTableLookup(CostTbl, ISDOpcode, LT.second);
|
|
|
|
if (Idx != -1)
|
|
return LT.first * CostTbl[Idx].Cost;
|
|
|
|
unsigned Cost = TargetTransformInfo::getArithmeticInstrCost(
|
|
Opcode, Ty, Op1Info, Op2Info, Opd1PropInfo, Opd2PropInfo);
|
|
|
|
// This is somewhat of a hack. The problem that we are facing is that SROA
|
|
// creates a sequence of shift, and, or instructions to construct values.
|
|
// These sequences are recognized by the ISel and have zero-cost. Not so for
|
|
// the vectorized code. Because we have support for v2i64 but not i64 those
|
|
// sequences look particularly beneficial to vectorize.
|
|
// To work around this we increase the cost of v2i64 operations to make them
|
|
// seem less beneficial.
|
|
if (LT.second == MVT::v2i64 &&
|
|
Op2Info == TargetTransformInfo::OK_UniformConstantValue)
|
|
Cost += 4;
|
|
|
|
return Cost;
|
|
}
|
|
|
|
unsigned ARMTTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
|
|
unsigned AddressSpace) const {
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
|
|
|
|
if (Src->isVectorTy() && Alignment != 16 &&
|
|
Src->getVectorElementType()->isDoubleTy()) {
|
|
// Unaligned loads/stores are extremely inefficient.
|
|
// We need 4 uops for vst.1/vld.1 vs 1uop for vldr/vstr.
|
|
return LT.first * 4;
|
|
}
|
|
return LT.first;
|
|
}
|