forked from OSchip/llvm-project
145 lines
6.5 KiB
C++
145 lines
6.5 KiB
C++
//===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the Machinelegalizer class for
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/// AMDGPU.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "AMDGPUArgumentUsageInfo.h"
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#include "SIInstrInfo.h"
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namespace llvm {
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class GCNTargetMachine;
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class LLVMContext;
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class GCNSubtarget;
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/// This class provides the information for the target register banks.
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class AMDGPULegalizerInfo : public LegalizerInfo {
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const GCNSubtarget &ST;
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public:
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AMDGPULegalizerInfo(const GCNSubtarget &ST,
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const GCNTargetMachine &TM);
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bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B,
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GISelChangeObserver &Observer) const override;
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Register getSegmentAperture(unsigned AddrSpace,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, bool Signed) const;
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bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, bool Signed) const;
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bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool buildPCRelGlobalAddress(
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Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV,
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unsigned Offset, unsigned GAFlags = SIInstrInfo::MO_NONE) const;
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bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B,
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GISelChangeObserver &Observer) const;
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bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B,
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double Log2BaseInverted) const;
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Register getLiveInRegister(MachineRegisterInfo &MRI,
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Register Reg, LLT Ty) const;
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bool loadInputValue(Register DstReg, MachineIRBuilder &B,
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const ArgDescriptor *Arg) const;
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bool legalizePreloadedArgIntrin(
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MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
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AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
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bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, unsigned AddrSpace) const;
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std::tuple<Register, unsigned, unsigned>
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splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
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Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
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Register Reg) const;
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bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, bool IsFormat) const;
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bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, bool IsFormat) const;
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Register fixStoreSourceType(MachineIRBuilder &B, Register VData,
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bool IsFormat) const;
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bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, bool IsTyped,
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bool IsFormat) const;
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bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, bool IsTyped,
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bool IsFormat) const;
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bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B,
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Intrinsic::ID IID) const;
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bool legalizeImageIntrinsic(
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MachineInstr &MI, MachineIRBuilder &B,
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GISelChangeObserver &Observer,
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const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const;
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bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B,
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bool IsInc) const;
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bool legalizeIntrinsic(MachineInstr &MI, MachineIRBuilder &B,
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GISelChangeObserver &Observer) const override;
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};
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} // End llvm namespace.
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#endif
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