forked from OSchip/llvm-project
1547 lines
54 KiB
C++
1547 lines
54 KiB
C++
//===-- SIFoldOperands.cpp - Fold operands --- ----------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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/// \file
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//===----------------------------------------------------------------------===//
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//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#define DEBUG_TYPE "si-fold-operands"
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using namespace llvm;
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namespace {
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struct FoldCandidate {
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MachineInstr *UseMI;
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union {
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MachineOperand *OpToFold;
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uint64_t ImmToFold;
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int FrameIndexToFold;
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};
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int ShrinkOpcode;
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unsigned char UseOpNo;
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MachineOperand::MachineOperandType Kind;
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bool Commuted;
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FoldCandidate(MachineInstr *MI, unsigned OpNo, MachineOperand *FoldOp,
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bool Commuted_ = false,
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int ShrinkOp = -1) :
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UseMI(MI), OpToFold(nullptr), ShrinkOpcode(ShrinkOp), UseOpNo(OpNo),
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Kind(FoldOp->getType()),
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Commuted(Commuted_) {
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if (FoldOp->isImm()) {
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ImmToFold = FoldOp->getImm();
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} else if (FoldOp->isFI()) {
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FrameIndexToFold = FoldOp->getIndex();
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} else {
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assert(FoldOp->isReg() || FoldOp->isGlobal());
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OpToFold = FoldOp;
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}
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}
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bool isFI() const {
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return Kind == MachineOperand::MO_FrameIndex;
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}
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bool isImm() const {
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return Kind == MachineOperand::MO_Immediate;
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}
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bool isReg() const {
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return Kind == MachineOperand::MO_Register;
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}
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bool isGlobal() const { return Kind == MachineOperand::MO_GlobalAddress; }
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bool isCommuted() const {
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return Commuted;
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}
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bool needsShrink() const {
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return ShrinkOpcode != -1;
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}
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int getShrinkOpcode() const {
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return ShrinkOpcode;
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}
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};
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class SIFoldOperands : public MachineFunctionPass {
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public:
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static char ID;
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MachineRegisterInfo *MRI;
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const SIInstrInfo *TII;
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const SIRegisterInfo *TRI;
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const GCNSubtarget *ST;
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const SIMachineFunctionInfo *MFI;
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void foldOperand(MachineOperand &OpToFold,
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MachineInstr *UseMI,
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int UseOpIdx,
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SmallVectorImpl<FoldCandidate> &FoldList,
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SmallVectorImpl<MachineInstr *> &CopiesToReplace) const;
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void foldInstOperand(MachineInstr &MI, MachineOperand &OpToFold) const;
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const MachineOperand *isClamp(const MachineInstr &MI) const;
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bool tryFoldClamp(MachineInstr &MI);
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std::pair<const MachineOperand *, int> isOMod(const MachineInstr &MI) const;
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bool tryFoldOMod(MachineInstr &MI);
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public:
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SIFoldOperands() : MachineFunctionPass(ID) {
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initializeSIFoldOperandsPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "SI Fold Operands"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS(SIFoldOperands, DEBUG_TYPE,
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"SI Fold Operands", false, false)
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char SIFoldOperands::ID = 0;
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char &llvm::SIFoldOperandsID = SIFoldOperands::ID;
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// Wrapper around isInlineConstant that understands special cases when
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// instruction types are replaced during operand folding.
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static bool isInlineConstantIfFolded(const SIInstrInfo *TII,
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const MachineInstr &UseMI,
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unsigned OpNo,
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const MachineOperand &OpToFold) {
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if (TII->isInlineConstant(UseMI, OpNo, OpToFold))
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return true;
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unsigned Opc = UseMI.getOpcode();
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switch (Opc) {
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case AMDGPU::V_MAC_F32_e64:
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case AMDGPU::V_MAC_F16_e64:
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case AMDGPU::V_FMAC_F32_e64:
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case AMDGPU::V_FMAC_F16_e64: {
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// Special case for mac. Since this is replaced with mad when folded into
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// src2, we need to check the legality for the final instruction.
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int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
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if (static_cast<int>(OpNo) == Src2Idx) {
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bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e64 ||
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Opc == AMDGPU::V_FMAC_F16_e64;
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bool IsF32 = Opc == AMDGPU::V_MAC_F32_e64 ||
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Opc == AMDGPU::V_FMAC_F32_e64;
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unsigned Opc = IsFMA ?
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(IsF32 ? AMDGPU::V_FMA_F32 : AMDGPU::V_FMA_F16_gfx9) :
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(IsF32 ? AMDGPU::V_MAD_F32 : AMDGPU::V_MAD_F16);
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const MCInstrDesc &MadDesc = TII->get(Opc);
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return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType);
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}
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return false;
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}
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default:
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return false;
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}
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}
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// TODO: Add heuristic that the frame index might not fit in the addressing mode
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// immediate offset to avoid materializing in loops.
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static bool frameIndexMayFold(const SIInstrInfo *TII,
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const MachineInstr &UseMI,
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int OpNo,
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const MachineOperand &OpToFold) {
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return OpToFold.isFI() &&
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(TII->isMUBUF(UseMI) || TII->isFLATScratch(UseMI)) &&
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OpNo == AMDGPU::getNamedOperandIdx(UseMI.getOpcode(), AMDGPU::OpName::vaddr);
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}
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FunctionPass *llvm::createSIFoldOperandsPass() {
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return new SIFoldOperands();
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}
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static bool updateOperand(FoldCandidate &Fold,
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const SIInstrInfo &TII,
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const TargetRegisterInfo &TRI,
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const GCNSubtarget &ST) {
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MachineInstr *MI = Fold.UseMI;
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MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
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assert(Old.isReg());
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if (Fold.isImm()) {
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if (MI->getDesc().TSFlags & SIInstrFlags::IsPacked &&
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!(MI->getDesc().TSFlags & SIInstrFlags::IsMAI) &&
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AMDGPU::isInlinableLiteralV216(static_cast<uint16_t>(Fold.ImmToFold),
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ST.hasInv2PiInlineImm())) {
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// Set op_sel/op_sel_hi on this operand or bail out if op_sel is
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// already set.
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unsigned Opcode = MI->getOpcode();
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int OpNo = MI->getOperandNo(&Old);
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int ModIdx = -1;
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if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0))
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ModIdx = AMDGPU::OpName::src0_modifiers;
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else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1))
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ModIdx = AMDGPU::OpName::src1_modifiers;
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else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2))
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ModIdx = AMDGPU::OpName::src2_modifiers;
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assert(ModIdx != -1);
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ModIdx = AMDGPU::getNamedOperandIdx(Opcode, ModIdx);
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MachineOperand &Mod = MI->getOperand(ModIdx);
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unsigned Val = Mod.getImm();
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if ((Val & SISrcMods::OP_SEL_0) || !(Val & SISrcMods::OP_SEL_1))
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return false;
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// Only apply the following transformation if that operand requries
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// a packed immediate.
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switch (TII.get(Opcode).OpInfo[OpNo].OperandType) {
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case AMDGPU::OPERAND_REG_IMM_V2FP16:
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case AMDGPU::OPERAND_REG_IMM_V2INT16:
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case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
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case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
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// If upper part is all zero we do not need op_sel_hi.
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if (!isUInt<16>(Fold.ImmToFold)) {
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if (!(Fold.ImmToFold & 0xffff)) {
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Mod.setImm(Mod.getImm() | SISrcMods::OP_SEL_0);
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Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1);
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Old.ChangeToImmediate((Fold.ImmToFold >> 16) & 0xffff);
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return true;
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}
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Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1);
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Old.ChangeToImmediate(Fold.ImmToFold & 0xffff);
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return true;
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}
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break;
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default:
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break;
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}
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}
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}
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if ((Fold.isImm() || Fold.isFI() || Fold.isGlobal()) && Fold.needsShrink()) {
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MachineBasicBlock *MBB = MI->getParent();
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auto Liveness = MBB->computeRegisterLiveness(&TRI, AMDGPU::VCC, MI, 16);
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if (Liveness != MachineBasicBlock::LQR_Dead) {
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LLVM_DEBUG(dbgs() << "Not shrinking " << MI << " due to vcc liveness\n");
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return false;
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}
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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int Op32 = Fold.getShrinkOpcode();
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MachineOperand &Dst0 = MI->getOperand(0);
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MachineOperand &Dst1 = MI->getOperand(1);
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assert(Dst0.isDef() && Dst1.isDef());
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bool HaveNonDbgCarryUse = !MRI.use_nodbg_empty(Dst1.getReg());
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const TargetRegisterClass *Dst0RC = MRI.getRegClass(Dst0.getReg());
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Register NewReg0 = MRI.createVirtualRegister(Dst0RC);
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MachineInstr *Inst32 = TII.buildShrunkInst(*MI, Op32);
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if (HaveNonDbgCarryUse) {
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BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), Dst1.getReg())
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.addReg(AMDGPU::VCC, RegState::Kill);
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}
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// Keep the old instruction around to avoid breaking iterators, but
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// replace it with a dummy instruction to remove uses.
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//
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// FIXME: We should not invert how this pass looks at operands to avoid
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// this. Should track set of foldable movs instead of looking for uses
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// when looking at a use.
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Dst0.setReg(NewReg0);
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for (unsigned I = MI->getNumOperands() - 1; I > 0; --I)
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MI->RemoveOperand(I);
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MI->setDesc(TII.get(AMDGPU::IMPLICIT_DEF));
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if (Fold.isCommuted())
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TII.commuteInstruction(*Inst32, false);
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return true;
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}
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assert(!Fold.needsShrink() && "not handled");
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if (Fold.isImm()) {
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Old.ChangeToImmediate(Fold.ImmToFold);
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return true;
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}
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if (Fold.isGlobal()) {
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Old.ChangeToGA(Fold.OpToFold->getGlobal(), Fold.OpToFold->getOffset(),
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Fold.OpToFold->getTargetFlags());
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return true;
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}
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if (Fold.isFI()) {
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Old.ChangeToFrameIndex(Fold.FrameIndexToFold);
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return true;
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}
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MachineOperand *New = Fold.OpToFold;
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Old.substVirtReg(New->getReg(), New->getSubReg(), TRI);
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Old.setIsUndef(New->isUndef());
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return true;
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}
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static bool isUseMIInFoldList(ArrayRef<FoldCandidate> FoldList,
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const MachineInstr *MI) {
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for (auto Candidate : FoldList) {
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if (Candidate.UseMI == MI)
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return true;
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}
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return false;
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}
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static void appendFoldCandidate(SmallVectorImpl<FoldCandidate> &FoldList,
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MachineInstr *MI, unsigned OpNo,
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MachineOperand *FoldOp, bool Commuted = false,
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int ShrinkOp = -1) {
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// Skip additional folding on the same operand.
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for (FoldCandidate &Fold : FoldList)
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if (Fold.UseMI == MI && Fold.UseOpNo == OpNo)
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return;
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LLVM_DEBUG(dbgs() << "Append " << (Commuted ? "commuted" : "normal")
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<< " operand " << OpNo << "\n " << *MI << '\n');
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FoldList.push_back(FoldCandidate(MI, OpNo, FoldOp, Commuted, ShrinkOp));
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}
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static bool tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
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MachineInstr *MI, unsigned OpNo,
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MachineOperand *OpToFold,
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const SIInstrInfo *TII) {
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if (!TII->isOperandLegal(*MI, OpNo, OpToFold)) {
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// Special case for v_mac_{f16, f32}_e64 if we are trying to fold into src2
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unsigned Opc = MI->getOpcode();
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if ((Opc == AMDGPU::V_MAC_F32_e64 || Opc == AMDGPU::V_MAC_F16_e64 ||
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Opc == AMDGPU::V_FMAC_F32_e64 || Opc == AMDGPU::V_FMAC_F16_e64) &&
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(int)OpNo == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)) {
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bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e64 ||
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Opc == AMDGPU::V_FMAC_F16_e64;
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bool IsF32 = Opc == AMDGPU::V_MAC_F32_e64 ||
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Opc == AMDGPU::V_FMAC_F32_e64;
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unsigned NewOpc = IsFMA ?
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(IsF32 ? AMDGPU::V_FMA_F32 : AMDGPU::V_FMA_F16_gfx9) :
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(IsF32 ? AMDGPU::V_MAD_F32 : AMDGPU::V_MAD_F16);
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// Check if changing this to a v_mad_{f16, f32} instruction will allow us
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// to fold the operand.
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MI->setDesc(TII->get(NewOpc));
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bool FoldAsMAD = tryAddToFoldList(FoldList, MI, OpNo, OpToFold, TII);
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if (FoldAsMAD) {
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MI->untieRegOperand(OpNo);
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return true;
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}
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MI->setDesc(TII->get(Opc));
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}
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// Special case for s_setreg_b32
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if (Opc == AMDGPU::S_SETREG_B32 && OpToFold->isImm()) {
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MI->setDesc(TII->get(AMDGPU::S_SETREG_IMM32_B32));
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appendFoldCandidate(FoldList, MI, OpNo, OpToFold);
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return true;
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}
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// If we are already folding into another operand of MI, then
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// we can't commute the instruction, otherwise we risk making the
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// other fold illegal.
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if (isUseMIInFoldList(FoldList, MI))
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return false;
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unsigned CommuteOpNo = OpNo;
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// Operand is not legal, so try to commute the instruction to
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// see if this makes it possible to fold.
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unsigned CommuteIdx0 = TargetInstrInfo::CommuteAnyOperandIndex;
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unsigned CommuteIdx1 = TargetInstrInfo::CommuteAnyOperandIndex;
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bool CanCommute = TII->findCommutedOpIndices(*MI, CommuteIdx0, CommuteIdx1);
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if (CanCommute) {
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if (CommuteIdx0 == OpNo)
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CommuteOpNo = CommuteIdx1;
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else if (CommuteIdx1 == OpNo)
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CommuteOpNo = CommuteIdx0;
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}
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// One of operands might be an Imm operand, and OpNo may refer to it after
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// the call of commuteInstruction() below. Such situations are avoided
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// here explicitly as OpNo must be a register operand to be a candidate
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// for memory folding.
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if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() ||
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!MI->getOperand(CommuteIdx1).isReg()))
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return false;
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if (!CanCommute ||
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!TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1))
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return false;
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if (!TII->isOperandLegal(*MI, CommuteOpNo, OpToFold)) {
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if ((Opc == AMDGPU::V_ADD_I32_e64 ||
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Opc == AMDGPU::V_SUB_I32_e64 ||
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Opc == AMDGPU::V_SUBREV_I32_e64) && // FIXME
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(OpToFold->isImm() || OpToFold->isFI() || OpToFold->isGlobal())) {
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MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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// Verify the other operand is a VGPR, otherwise we would violate the
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// constant bus restriction.
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unsigned OtherIdx = CommuteOpNo == CommuteIdx0 ? CommuteIdx1 : CommuteIdx0;
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MachineOperand &OtherOp = MI->getOperand(OtherIdx);
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if (!OtherOp.isReg() ||
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!TII->getRegisterInfo().isVGPR(MRI, OtherOp.getReg()))
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return false;
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assert(MI->getOperand(1).isDef());
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// Make sure to get the 32-bit version of the commuted opcode.
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unsigned MaybeCommutedOpc = MI->getOpcode();
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int Op32 = AMDGPU::getVOPe32(MaybeCommutedOpc);
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appendFoldCandidate(FoldList, MI, CommuteOpNo, OpToFold, true, Op32);
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return true;
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}
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TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1);
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return false;
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}
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appendFoldCandidate(FoldList, MI, CommuteOpNo, OpToFold, true);
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return true;
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}
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// Check the case where we might introduce a second constant operand to a
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// scalar instruction
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if (TII->isSALU(MI->getOpcode())) {
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const MCInstrDesc &InstDesc = MI->getDesc();
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const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];
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const SIRegisterInfo &SRI = TII->getRegisterInfo();
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// Fine if the operand can be encoded as an inline constant
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if (OpToFold->isImm()) {
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if (!SRI.opCanUseInlineConstant(OpInfo.OperandType) ||
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!TII->isInlineConstant(*OpToFold, OpInfo)) {
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// Otherwise check for another constant
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for (unsigned i = 0, e = InstDesc.getNumOperands(); i != e; ++i) {
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auto &Op = MI->getOperand(i);
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if (OpNo != i &&
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TII->isLiteralConstantLike(Op, OpInfo)) {
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return false;
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}
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}
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}
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}
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}
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appendFoldCandidate(FoldList, MI, OpNo, OpToFold);
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return true;
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}
|
|
|
|
// If the use operand doesn't care about the value, this may be an operand only
|
|
// used for register indexing, in which case it is unsafe to fold.
|
|
static bool isUseSafeToFold(const SIInstrInfo *TII,
|
|
const MachineInstr &MI,
|
|
const MachineOperand &UseMO) {
|
|
return !UseMO.isUndef() && !TII->isSDWA(MI);
|
|
//return !MI.hasRegisterImplicitUseOperand(UseMO.getReg());
|
|
}
|
|
|
|
// Find a def of the UseReg, check if it is a reg_seqence and find initializers
|
|
// for each subreg, tracking it to foldable inline immediate if possible.
|
|
// Returns true on success.
|
|
static bool getRegSeqInit(
|
|
SmallVectorImpl<std::pair<MachineOperand*, unsigned>> &Defs,
|
|
Register UseReg, uint8_t OpTy,
|
|
const SIInstrInfo *TII, const MachineRegisterInfo &MRI) {
|
|
MachineInstr *Def = MRI.getUniqueVRegDef(UseReg);
|
|
if (!Def || !Def->isRegSequence())
|
|
return false;
|
|
|
|
for (unsigned I = 1, E = Def->getNumExplicitOperands(); I < E; I += 2) {
|
|
MachineOperand *Sub = &Def->getOperand(I);
|
|
assert (Sub->isReg());
|
|
|
|
for (MachineInstr *SubDef = MRI.getUniqueVRegDef(Sub->getReg());
|
|
SubDef && Sub->isReg() && !Sub->getSubReg() &&
|
|
TII->isFoldableCopy(*SubDef);
|
|
SubDef = MRI.getUniqueVRegDef(Sub->getReg())) {
|
|
MachineOperand *Op = &SubDef->getOperand(1);
|
|
if (Op->isImm()) {
|
|
if (TII->isInlineConstant(*Op, OpTy))
|
|
Sub = Op;
|
|
break;
|
|
}
|
|
if (!Op->isReg())
|
|
break;
|
|
Sub = Op;
|
|
}
|
|
|
|
Defs.push_back(std::make_pair(Sub, Def->getOperand(I + 1).getImm()));
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool tryToFoldACImm(const SIInstrInfo *TII,
|
|
const MachineOperand &OpToFold,
|
|
MachineInstr *UseMI,
|
|
unsigned UseOpIdx,
|
|
SmallVectorImpl<FoldCandidate> &FoldList) {
|
|
const MCInstrDesc &Desc = UseMI->getDesc();
|
|
const MCOperandInfo *OpInfo = Desc.OpInfo;
|
|
if (!OpInfo || UseOpIdx >= Desc.getNumOperands())
|
|
return false;
|
|
|
|
uint8_t OpTy = OpInfo[UseOpIdx].OperandType;
|
|
if (OpTy < AMDGPU::OPERAND_REG_INLINE_AC_FIRST ||
|
|
OpTy > AMDGPU::OPERAND_REG_INLINE_AC_LAST)
|
|
return false;
|
|
|
|
if (OpToFold.isImm() && TII->isInlineConstant(OpToFold, OpTy) &&
|
|
TII->isOperandLegal(*UseMI, UseOpIdx, &OpToFold)) {
|
|
UseMI->getOperand(UseOpIdx).ChangeToImmediate(OpToFold.getImm());
|
|
return true;
|
|
}
|
|
|
|
if (!OpToFold.isReg())
|
|
return false;
|
|
|
|
Register UseReg = OpToFold.getReg();
|
|
if (!Register::isVirtualRegister(UseReg))
|
|
return false;
|
|
|
|
if (llvm::find_if(FoldList, [UseMI](const FoldCandidate &FC) {
|
|
return FC.UseMI == UseMI; }) != FoldList.end())
|
|
return false;
|
|
|
|
MachineRegisterInfo &MRI = UseMI->getParent()->getParent()->getRegInfo();
|
|
SmallVector<std::pair<MachineOperand*, unsigned>, 32> Defs;
|
|
if (!getRegSeqInit(Defs, UseReg, OpTy, TII, MRI))
|
|
return false;
|
|
|
|
int32_t Imm;
|
|
for (unsigned I = 0, E = Defs.size(); I != E; ++I) {
|
|
const MachineOperand *Op = Defs[I].first;
|
|
if (!Op->isImm())
|
|
return false;
|
|
|
|
auto SubImm = Op->getImm();
|
|
if (!I) {
|
|
Imm = SubImm;
|
|
if (!TII->isInlineConstant(*Op, OpTy) ||
|
|
!TII->isOperandLegal(*UseMI, UseOpIdx, Op))
|
|
return false;
|
|
|
|
continue;
|
|
}
|
|
if (Imm != SubImm)
|
|
return false; // Can only fold splat constants
|
|
}
|
|
|
|
appendFoldCandidate(FoldList, UseMI, UseOpIdx, Defs[0].first);
|
|
return true;
|
|
}
|
|
|
|
void SIFoldOperands::foldOperand(
|
|
MachineOperand &OpToFold,
|
|
MachineInstr *UseMI,
|
|
int UseOpIdx,
|
|
SmallVectorImpl<FoldCandidate> &FoldList,
|
|
SmallVectorImpl<MachineInstr *> &CopiesToReplace) const {
|
|
const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx);
|
|
|
|
if (!isUseSafeToFold(TII, *UseMI, UseOp))
|
|
return;
|
|
|
|
// FIXME: Fold operands with subregs.
|
|
if (UseOp.isReg() && OpToFold.isReg()) {
|
|
if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister)
|
|
return;
|
|
}
|
|
|
|
// Special case for REG_SEQUENCE: We can't fold literals into
|
|
// REG_SEQUENCE instructions, so we have to fold them into the
|
|
// uses of REG_SEQUENCE.
|
|
if (UseMI->isRegSequence()) {
|
|
Register RegSeqDstReg = UseMI->getOperand(0).getReg();
|
|
unsigned RegSeqDstSubReg = UseMI->getOperand(UseOpIdx + 1).getImm();
|
|
|
|
MachineRegisterInfo::use_iterator Next;
|
|
for (MachineRegisterInfo::use_iterator
|
|
RSUse = MRI->use_begin(RegSeqDstReg), RSE = MRI->use_end();
|
|
RSUse != RSE; RSUse = Next) {
|
|
Next = std::next(RSUse);
|
|
|
|
MachineInstr *RSUseMI = RSUse->getParent();
|
|
|
|
if (tryToFoldACImm(TII, UseMI->getOperand(0), RSUseMI,
|
|
RSUse.getOperandNo(), FoldList))
|
|
continue;
|
|
|
|
if (RSUse->getSubReg() != RegSeqDstSubReg)
|
|
continue;
|
|
|
|
foldOperand(OpToFold, RSUseMI, RSUse.getOperandNo(), FoldList,
|
|
CopiesToReplace);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
if (tryToFoldACImm(TII, OpToFold, UseMI, UseOpIdx, FoldList))
|
|
return;
|
|
|
|
if (frameIndexMayFold(TII, *UseMI, UseOpIdx, OpToFold)) {
|
|
// Sanity check that this is a stack access.
|
|
// FIXME: Should probably use stack pseudos before frame lowering.
|
|
MachineOperand *SOff = TII->getNamedOperand(*UseMI, AMDGPU::OpName::soffset);
|
|
if (!SOff->isReg() || (SOff->getReg() != MFI->getScratchWaveOffsetReg() &&
|
|
SOff->getReg() != MFI->getStackPtrOffsetReg()))
|
|
return;
|
|
|
|
if (TII->getNamedOperand(*UseMI, AMDGPU::OpName::srsrc)->getReg() !=
|
|
MFI->getScratchRSrcReg())
|
|
return;
|
|
|
|
// A frame index will resolve to a positive constant, so it should always be
|
|
// safe to fold the addressing mode, even pre-GFX9.
|
|
UseMI->getOperand(UseOpIdx).ChangeToFrameIndex(OpToFold.getIndex());
|
|
SOff->setReg(MFI->getStackPtrOffsetReg());
|
|
return;
|
|
}
|
|
|
|
bool FoldingImmLike =
|
|
OpToFold.isImm() || OpToFold.isFI() || OpToFold.isGlobal();
|
|
|
|
if (FoldingImmLike && UseMI->isCopy()) {
|
|
Register DestReg = UseMI->getOperand(0).getReg();
|
|
|
|
// Don't fold into a copy to a physical register. Doing so would interfere
|
|
// with the register coalescer's logic which would avoid redundant
|
|
// initalizations.
|
|
if (DestReg.isPhysical())
|
|
return;
|
|
|
|
const TargetRegisterClass *DestRC = MRI->getRegClass(DestReg);
|
|
|
|
Register SrcReg = UseMI->getOperand(1).getReg();
|
|
if (SrcReg.isVirtual()) { // XXX - This can be an assert?
|
|
const TargetRegisterClass * SrcRC = MRI->getRegClass(SrcReg);
|
|
if (TRI->isSGPRClass(SrcRC) && TRI->hasVectorRegisters(DestRC)) {
|
|
MachineRegisterInfo::use_iterator NextUse;
|
|
SmallVector<FoldCandidate, 4> CopyUses;
|
|
for (MachineRegisterInfo::use_iterator
|
|
Use = MRI->use_begin(DestReg), E = MRI->use_end();
|
|
Use != E; Use = NextUse) {
|
|
NextUse = std::next(Use);
|
|
FoldCandidate FC = FoldCandidate(Use->getParent(),
|
|
Use.getOperandNo(), &UseMI->getOperand(1));
|
|
CopyUses.push_back(FC);
|
|
}
|
|
for (auto & F : CopyUses) {
|
|
foldOperand(*F.OpToFold, F.UseMI, F.UseOpNo,
|
|
FoldList, CopiesToReplace);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (DestRC == &AMDGPU::AGPR_32RegClass &&
|
|
TII->isInlineConstant(OpToFold, AMDGPU::OPERAND_REG_INLINE_C_INT32)) {
|
|
UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32));
|
|
UseMI->getOperand(1).ChangeToImmediate(OpToFold.getImm());
|
|
CopiesToReplace.push_back(UseMI);
|
|
return;
|
|
}
|
|
|
|
// In order to fold immediates into copies, we need to change the
|
|
// copy to a MOV.
|
|
|
|
unsigned MovOp = TII->getMovOpcode(DestRC);
|
|
if (MovOp == AMDGPU::COPY)
|
|
return;
|
|
|
|
UseMI->setDesc(TII->get(MovOp));
|
|
MachineInstr::mop_iterator ImpOpI = UseMI->implicit_operands().begin();
|
|
MachineInstr::mop_iterator ImpOpE = UseMI->implicit_operands().end();
|
|
while (ImpOpI != ImpOpE) {
|
|
MachineInstr::mop_iterator Tmp = ImpOpI;
|
|
ImpOpI++;
|
|
UseMI->RemoveOperand(UseMI->getOperandNo(Tmp));
|
|
}
|
|
CopiesToReplace.push_back(UseMI);
|
|
} else {
|
|
if (UseMI->isCopy() && OpToFold.isReg() &&
|
|
UseMI->getOperand(0).getReg().isVirtual() &&
|
|
!UseMI->getOperand(1).getSubReg()) {
|
|
LLVM_DEBUG(dbgs() << "Folding " << OpToFold
|
|
<< "\n into " << *UseMI << '\n');
|
|
unsigned Size = TII->getOpSize(*UseMI, 1);
|
|
Register UseReg = OpToFold.getReg();
|
|
UseMI->getOperand(1).setReg(UseReg);
|
|
UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
|
|
UseMI->getOperand(1).setIsKill(false);
|
|
CopiesToReplace.push_back(UseMI);
|
|
OpToFold.setIsKill(false);
|
|
|
|
// That is very tricky to store a value into an AGPR. v_accvgpr_write_b32
|
|
// can only accept VGPR or inline immediate. Recreate a reg_sequence with
|
|
// its initializers right here, so we will rematerialize immediates and
|
|
// avoid copies via different reg classes.
|
|
SmallVector<std::pair<MachineOperand*, unsigned>, 32> Defs;
|
|
if (Size > 4 && TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg()) &&
|
|
getRegSeqInit(Defs, UseReg, AMDGPU::OPERAND_REG_INLINE_C_INT32, TII,
|
|
*MRI)) {
|
|
const DebugLoc &DL = UseMI->getDebugLoc();
|
|
MachineBasicBlock &MBB = *UseMI->getParent();
|
|
|
|
UseMI->setDesc(TII->get(AMDGPU::REG_SEQUENCE));
|
|
for (unsigned I = UseMI->getNumOperands() - 1; I > 0; --I)
|
|
UseMI->RemoveOperand(I);
|
|
|
|
MachineInstrBuilder B(*MBB.getParent(), UseMI);
|
|
DenseMap<TargetInstrInfo::RegSubRegPair, Register> VGPRCopies;
|
|
SmallSetVector<TargetInstrInfo::RegSubRegPair, 32> SeenAGPRs;
|
|
for (unsigned I = 0; I < Size / 4; ++I) {
|
|
MachineOperand *Def = Defs[I].first;
|
|
TargetInstrInfo::RegSubRegPair CopyToVGPR;
|
|
if (Def->isImm() &&
|
|
TII->isInlineConstant(*Def, AMDGPU::OPERAND_REG_INLINE_C_INT32)) {
|
|
int64_t Imm = Def->getImm();
|
|
|
|
auto Tmp = MRI->createVirtualRegister(&AMDGPU::AGPR_32RegClass);
|
|
BuildMI(MBB, UseMI, DL,
|
|
TII->get(AMDGPU::V_ACCVGPR_WRITE_B32), Tmp).addImm(Imm);
|
|
B.addReg(Tmp);
|
|
} else if (Def->isReg() && TRI->isAGPR(*MRI, Def->getReg())) {
|
|
auto Src = getRegSubRegPair(*Def);
|
|
Def->setIsKill(false);
|
|
if (!SeenAGPRs.insert(Src)) {
|
|
// We cannot build a reg_sequence out of the same registers, they
|
|
// must be copied. Better do it here before copyPhysReg() created
|
|
// several reads to do the AGPR->VGPR->AGPR copy.
|
|
CopyToVGPR = Src;
|
|
} else {
|
|
B.addReg(Src.Reg, Def->isUndef() ? RegState::Undef : 0,
|
|
Src.SubReg);
|
|
}
|
|
} else {
|
|
assert(Def->isReg());
|
|
Def->setIsKill(false);
|
|
auto Src = getRegSubRegPair(*Def);
|
|
|
|
// Direct copy from SGPR to AGPR is not possible. To avoid creation
|
|
// of exploded copies SGPR->VGPR->AGPR in the copyPhysReg() later,
|
|
// create a copy here and track if we already have such a copy.
|
|
if (TRI->isSGPRReg(*MRI, Src.Reg)) {
|
|
CopyToVGPR = Src;
|
|
} else {
|
|
auto Tmp = MRI->createVirtualRegister(&AMDGPU::AGPR_32RegClass);
|
|
BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Tmp).add(*Def);
|
|
B.addReg(Tmp);
|
|
}
|
|
}
|
|
|
|
if (CopyToVGPR.Reg) {
|
|
Register Vgpr;
|
|
if (VGPRCopies.count(CopyToVGPR)) {
|
|
Vgpr = VGPRCopies[CopyToVGPR];
|
|
} else {
|
|
Vgpr = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
|
|
BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Vgpr).add(*Def);
|
|
VGPRCopies[CopyToVGPR] = Vgpr;
|
|
}
|
|
auto Tmp = MRI->createVirtualRegister(&AMDGPU::AGPR_32RegClass);
|
|
BuildMI(MBB, UseMI, DL,
|
|
TII->get(AMDGPU::V_ACCVGPR_WRITE_B32), Tmp).addReg(Vgpr);
|
|
B.addReg(Tmp);
|
|
}
|
|
|
|
B.addImm(Defs[I].second);
|
|
}
|
|
LLVM_DEBUG(dbgs() << "Folded " << *UseMI << '\n');
|
|
return;
|
|
}
|
|
|
|
if (Size != 4)
|
|
return;
|
|
if (TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg()) &&
|
|
TRI->isVGPR(*MRI, UseMI->getOperand(1).getReg()))
|
|
UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32));
|
|
else if (TRI->isVGPR(*MRI, UseMI->getOperand(0).getReg()) &&
|
|
TRI->isAGPR(*MRI, UseMI->getOperand(1).getReg()))
|
|
UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_READ_B32));
|
|
return;
|
|
}
|
|
|
|
unsigned UseOpc = UseMI->getOpcode();
|
|
if (UseOpc == AMDGPU::V_READFIRSTLANE_B32 ||
|
|
(UseOpc == AMDGPU::V_READLANE_B32 &&
|
|
(int)UseOpIdx ==
|
|
AMDGPU::getNamedOperandIdx(UseOpc, AMDGPU::OpName::src0))) {
|
|
// %vgpr = V_MOV_B32 imm
|
|
// %sgpr = V_READFIRSTLANE_B32 %vgpr
|
|
// =>
|
|
// %sgpr = S_MOV_B32 imm
|
|
if (FoldingImmLike) {
|
|
if (execMayBeModifiedBeforeUse(*MRI,
|
|
UseMI->getOperand(UseOpIdx).getReg(),
|
|
*OpToFold.getParent(),
|
|
*UseMI))
|
|
return;
|
|
|
|
UseMI->setDesc(TII->get(AMDGPU::S_MOV_B32));
|
|
|
|
// FIXME: ChangeToImmediate should clear subreg
|
|
UseMI->getOperand(1).setSubReg(0);
|
|
if (OpToFold.isImm())
|
|
UseMI->getOperand(1).ChangeToImmediate(OpToFold.getImm());
|
|
else
|
|
UseMI->getOperand(1).ChangeToFrameIndex(OpToFold.getIndex());
|
|
UseMI->RemoveOperand(2); // Remove exec read (or src1 for readlane)
|
|
return;
|
|
}
|
|
|
|
if (OpToFold.isReg() && TRI->isSGPRReg(*MRI, OpToFold.getReg())) {
|
|
if (execMayBeModifiedBeforeUse(*MRI,
|
|
UseMI->getOperand(UseOpIdx).getReg(),
|
|
*OpToFold.getParent(),
|
|
*UseMI))
|
|
return;
|
|
|
|
// %vgpr = COPY %sgpr0
|
|
// %sgpr1 = V_READFIRSTLANE_B32 %vgpr
|
|
// =>
|
|
// %sgpr1 = COPY %sgpr0
|
|
UseMI->setDesc(TII->get(AMDGPU::COPY));
|
|
UseMI->getOperand(1).setReg(OpToFold.getReg());
|
|
UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
|
|
UseMI->getOperand(1).setIsKill(false);
|
|
UseMI->RemoveOperand(2); // Remove exec read (or src1 for readlane)
|
|
return;
|
|
}
|
|
}
|
|
|
|
const MCInstrDesc &UseDesc = UseMI->getDesc();
|
|
|
|
// Don't fold into target independent nodes. Target independent opcodes
|
|
// don't have defined register classes.
|
|
if (UseDesc.isVariadic() ||
|
|
UseOp.isImplicit() ||
|
|
UseDesc.OpInfo[UseOpIdx].RegClass == -1)
|
|
return;
|
|
}
|
|
|
|
if (!FoldingImmLike) {
|
|
tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII);
|
|
|
|
// FIXME: We could try to change the instruction from 64-bit to 32-bit
|
|
// to enable more folding opportunites. The shrink operands pass
|
|
// already does this.
|
|
return;
|
|
}
|
|
|
|
|
|
const MCInstrDesc &FoldDesc = OpToFold.getParent()->getDesc();
|
|
const TargetRegisterClass *FoldRC =
|
|
TRI->getRegClass(FoldDesc.OpInfo[0].RegClass);
|
|
|
|
// Split 64-bit constants into 32-bits for folding.
|
|
if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) {
|
|
Register UseReg = UseOp.getReg();
|
|
const TargetRegisterClass *UseRC = MRI->getRegClass(UseReg);
|
|
|
|
if (AMDGPU::getRegBitWidth(UseRC->getID()) != 64)
|
|
return;
|
|
|
|
APInt Imm(64, OpToFold.getImm());
|
|
if (UseOp.getSubReg() == AMDGPU::sub0) {
|
|
Imm = Imm.getLoBits(32);
|
|
} else {
|
|
assert(UseOp.getSubReg() == AMDGPU::sub1);
|
|
Imm = Imm.getHiBits(32);
|
|
}
|
|
|
|
MachineOperand ImmOp = MachineOperand::CreateImm(Imm.getSExtValue());
|
|
tryAddToFoldList(FoldList, UseMI, UseOpIdx, &ImmOp, TII);
|
|
return;
|
|
}
|
|
|
|
|
|
|
|
tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII);
|
|
}
|
|
|
|
static bool evalBinaryInstruction(unsigned Opcode, int32_t &Result,
|
|
uint32_t LHS, uint32_t RHS) {
|
|
switch (Opcode) {
|
|
case AMDGPU::V_AND_B32_e64:
|
|
case AMDGPU::V_AND_B32_e32:
|
|
case AMDGPU::S_AND_B32:
|
|
Result = LHS & RHS;
|
|
return true;
|
|
case AMDGPU::V_OR_B32_e64:
|
|
case AMDGPU::V_OR_B32_e32:
|
|
case AMDGPU::S_OR_B32:
|
|
Result = LHS | RHS;
|
|
return true;
|
|
case AMDGPU::V_XOR_B32_e64:
|
|
case AMDGPU::V_XOR_B32_e32:
|
|
case AMDGPU::S_XOR_B32:
|
|
Result = LHS ^ RHS;
|
|
return true;
|
|
case AMDGPU::V_LSHL_B32_e64:
|
|
case AMDGPU::V_LSHL_B32_e32:
|
|
case AMDGPU::S_LSHL_B32:
|
|
// The instruction ignores the high bits for out of bounds shifts.
|
|
Result = LHS << (RHS & 31);
|
|
return true;
|
|
case AMDGPU::V_LSHLREV_B32_e64:
|
|
case AMDGPU::V_LSHLREV_B32_e32:
|
|
Result = RHS << (LHS & 31);
|
|
return true;
|
|
case AMDGPU::V_LSHR_B32_e64:
|
|
case AMDGPU::V_LSHR_B32_e32:
|
|
case AMDGPU::S_LSHR_B32:
|
|
Result = LHS >> (RHS & 31);
|
|
return true;
|
|
case AMDGPU::V_LSHRREV_B32_e64:
|
|
case AMDGPU::V_LSHRREV_B32_e32:
|
|
Result = RHS >> (LHS & 31);
|
|
return true;
|
|
case AMDGPU::V_ASHR_I32_e64:
|
|
case AMDGPU::V_ASHR_I32_e32:
|
|
case AMDGPU::S_ASHR_I32:
|
|
Result = static_cast<int32_t>(LHS) >> (RHS & 31);
|
|
return true;
|
|
case AMDGPU::V_ASHRREV_I32_e64:
|
|
case AMDGPU::V_ASHRREV_I32_e32:
|
|
Result = static_cast<int32_t>(RHS) >> (LHS & 31);
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static unsigned getMovOpc(bool IsScalar) {
|
|
return IsScalar ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
|
|
}
|
|
|
|
/// Remove any leftover implicit operands from mutating the instruction. e.g.
|
|
/// if we replace an s_and_b32 with a copy, we don't need the implicit scc def
|
|
/// anymore.
|
|
static void stripExtraCopyOperands(MachineInstr &MI) {
|
|
const MCInstrDesc &Desc = MI.getDesc();
|
|
unsigned NumOps = Desc.getNumOperands() +
|
|
Desc.getNumImplicitUses() +
|
|
Desc.getNumImplicitDefs();
|
|
|
|
for (unsigned I = MI.getNumOperands() - 1; I >= NumOps; --I)
|
|
MI.RemoveOperand(I);
|
|
}
|
|
|
|
static void mutateCopyOp(MachineInstr &MI, const MCInstrDesc &NewDesc) {
|
|
MI.setDesc(NewDesc);
|
|
stripExtraCopyOperands(MI);
|
|
}
|
|
|
|
static MachineOperand *getImmOrMaterializedImm(MachineRegisterInfo &MRI,
|
|
MachineOperand &Op) {
|
|
if (Op.isReg()) {
|
|
// If this has a subregister, it obviously is a register source.
|
|
if (Op.getSubReg() != AMDGPU::NoSubRegister ||
|
|
!Register::isVirtualRegister(Op.getReg()))
|
|
return &Op;
|
|
|
|
MachineInstr *Def = MRI.getVRegDef(Op.getReg());
|
|
if (Def && Def->isMoveImmediate()) {
|
|
MachineOperand &ImmSrc = Def->getOperand(1);
|
|
if (ImmSrc.isImm())
|
|
return &ImmSrc;
|
|
}
|
|
}
|
|
|
|
return &Op;
|
|
}
|
|
|
|
// Try to simplify operations with a constant that may appear after instruction
|
|
// selection.
|
|
// TODO: See if a frame index with a fixed offset can fold.
|
|
static bool tryConstantFoldOp(MachineRegisterInfo &MRI,
|
|
const SIInstrInfo *TII,
|
|
MachineInstr *MI,
|
|
MachineOperand *ImmOp) {
|
|
unsigned Opc = MI->getOpcode();
|
|
if (Opc == AMDGPU::V_NOT_B32_e64 || Opc == AMDGPU::V_NOT_B32_e32 ||
|
|
Opc == AMDGPU::S_NOT_B32) {
|
|
MI->getOperand(1).ChangeToImmediate(~ImmOp->getImm());
|
|
mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_NOT_B32)));
|
|
return true;
|
|
}
|
|
|
|
int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
|
|
if (Src1Idx == -1)
|
|
return false;
|
|
|
|
int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
|
|
MachineOperand *Src0 = getImmOrMaterializedImm(MRI, MI->getOperand(Src0Idx));
|
|
MachineOperand *Src1 = getImmOrMaterializedImm(MRI, MI->getOperand(Src1Idx));
|
|
|
|
if (!Src0->isImm() && !Src1->isImm())
|
|
return false;
|
|
|
|
if (MI->getOpcode() == AMDGPU::V_LSHL_OR_B32) {
|
|
if (Src0->isImm() && Src0->getImm() == 0) {
|
|
// v_lshl_or_b32 0, X, Y -> copy Y
|
|
// v_lshl_or_b32 0, X, K -> v_mov_b32 K
|
|
bool UseCopy = TII->getNamedOperand(*MI, AMDGPU::OpName::src2)->isReg();
|
|
MI->RemoveOperand(Src1Idx);
|
|
MI->RemoveOperand(Src0Idx);
|
|
|
|
MI->setDesc(TII->get(UseCopy ? AMDGPU::COPY : AMDGPU::V_MOV_B32_e32));
|
|
return true;
|
|
}
|
|
}
|
|
|
|
// and k0, k1 -> v_mov_b32 (k0 & k1)
|
|
// or k0, k1 -> v_mov_b32 (k0 | k1)
|
|
// xor k0, k1 -> v_mov_b32 (k0 ^ k1)
|
|
if (Src0->isImm() && Src1->isImm()) {
|
|
int32_t NewImm;
|
|
if (!evalBinaryInstruction(Opc, NewImm, Src0->getImm(), Src1->getImm()))
|
|
return false;
|
|
|
|
const SIRegisterInfo &TRI = TII->getRegisterInfo();
|
|
bool IsSGPR = TRI.isSGPRReg(MRI, MI->getOperand(0).getReg());
|
|
|
|
// Be careful to change the right operand, src0 may belong to a different
|
|
// instruction.
|
|
MI->getOperand(Src0Idx).ChangeToImmediate(NewImm);
|
|
MI->RemoveOperand(Src1Idx);
|
|
mutateCopyOp(*MI, TII->get(getMovOpc(IsSGPR)));
|
|
return true;
|
|
}
|
|
|
|
if (!MI->isCommutable())
|
|
return false;
|
|
|
|
if (Src0->isImm() && !Src1->isImm()) {
|
|
std::swap(Src0, Src1);
|
|
std::swap(Src0Idx, Src1Idx);
|
|
}
|
|
|
|
int32_t Src1Val = static_cast<int32_t>(Src1->getImm());
|
|
if (Opc == AMDGPU::V_OR_B32_e64 ||
|
|
Opc == AMDGPU::V_OR_B32_e32 ||
|
|
Opc == AMDGPU::S_OR_B32) {
|
|
if (Src1Val == 0) {
|
|
// y = or x, 0 => y = copy x
|
|
MI->RemoveOperand(Src1Idx);
|
|
mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
|
|
} else if (Src1Val == -1) {
|
|
// y = or x, -1 => y = v_mov_b32 -1
|
|
MI->RemoveOperand(Src1Idx);
|
|
mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_OR_B32)));
|
|
} else
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
if (MI->getOpcode() == AMDGPU::V_AND_B32_e64 ||
|
|
MI->getOpcode() == AMDGPU::V_AND_B32_e32 ||
|
|
MI->getOpcode() == AMDGPU::S_AND_B32) {
|
|
if (Src1Val == 0) {
|
|
// y = and x, 0 => y = v_mov_b32 0
|
|
MI->RemoveOperand(Src0Idx);
|
|
mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_AND_B32)));
|
|
} else if (Src1Val == -1) {
|
|
// y = and x, -1 => y = copy x
|
|
MI->RemoveOperand(Src1Idx);
|
|
mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
|
|
stripExtraCopyOperands(*MI);
|
|
} else
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
if (MI->getOpcode() == AMDGPU::V_XOR_B32_e64 ||
|
|
MI->getOpcode() == AMDGPU::V_XOR_B32_e32 ||
|
|
MI->getOpcode() == AMDGPU::S_XOR_B32) {
|
|
if (Src1Val == 0) {
|
|
// y = xor x, 0 => y = copy x
|
|
MI->RemoveOperand(Src1Idx);
|
|
mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
|
|
return true;
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
// Try to fold an instruction into a simpler one
|
|
static bool tryFoldInst(const SIInstrInfo *TII,
|
|
MachineInstr *MI) {
|
|
unsigned Opc = MI->getOpcode();
|
|
|
|
if (Opc == AMDGPU::V_CNDMASK_B32_e32 ||
|
|
Opc == AMDGPU::V_CNDMASK_B32_e64 ||
|
|
Opc == AMDGPU::V_CNDMASK_B64_PSEUDO) {
|
|
const MachineOperand *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0);
|
|
const MachineOperand *Src1 = TII->getNamedOperand(*MI, AMDGPU::OpName::src1);
|
|
int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
|
|
int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
|
|
if (Src1->isIdenticalTo(*Src0) &&
|
|
(Src1ModIdx == -1 || !MI->getOperand(Src1ModIdx).getImm()) &&
|
|
(Src0ModIdx == -1 || !MI->getOperand(Src0ModIdx).getImm())) {
|
|
LLVM_DEBUG(dbgs() << "Folded " << *MI << " into ");
|
|
auto &NewDesc =
|
|
TII->get(Src0->isReg() ? (unsigned)AMDGPU::COPY : getMovOpc(false));
|
|
int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
|
|
if (Src2Idx != -1)
|
|
MI->RemoveOperand(Src2Idx);
|
|
MI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1));
|
|
if (Src1ModIdx != -1)
|
|
MI->RemoveOperand(Src1ModIdx);
|
|
if (Src0ModIdx != -1)
|
|
MI->RemoveOperand(Src0ModIdx);
|
|
mutateCopyOp(*MI, NewDesc);
|
|
LLVM_DEBUG(dbgs() << *MI << '\n');
|
|
return true;
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
void SIFoldOperands::foldInstOperand(MachineInstr &MI,
|
|
MachineOperand &OpToFold) const {
|
|
// We need mutate the operands of new mov instructions to add implicit
|
|
// uses of EXEC, but adding them invalidates the use_iterator, so defer
|
|
// this.
|
|
SmallVector<MachineInstr *, 4> CopiesToReplace;
|
|
SmallVector<FoldCandidate, 4> FoldList;
|
|
MachineOperand &Dst = MI.getOperand(0);
|
|
|
|
bool FoldingImm = OpToFold.isImm() || OpToFold.isFI() || OpToFold.isGlobal();
|
|
if (FoldingImm) {
|
|
unsigned NumLiteralUses = 0;
|
|
MachineOperand *NonInlineUse = nullptr;
|
|
int NonInlineUseOpNo = -1;
|
|
|
|
MachineRegisterInfo::use_iterator NextUse;
|
|
for (MachineRegisterInfo::use_iterator
|
|
Use = MRI->use_begin(Dst.getReg()), E = MRI->use_end();
|
|
Use != E; Use = NextUse) {
|
|
NextUse = std::next(Use);
|
|
MachineInstr *UseMI = Use->getParent();
|
|
unsigned OpNo = Use.getOperandNo();
|
|
|
|
// Folding the immediate may reveal operations that can be constant
|
|
// folded or replaced with a copy. This can happen for example after
|
|
// frame indices are lowered to constants or from splitting 64-bit
|
|
// constants.
|
|
//
|
|
// We may also encounter cases where one or both operands are
|
|
// immediates materialized into a register, which would ordinarily not
|
|
// be folded due to multiple uses or operand constraints.
|
|
|
|
if (OpToFold.isImm() && tryConstantFoldOp(*MRI, TII, UseMI, &OpToFold)) {
|
|
LLVM_DEBUG(dbgs() << "Constant folded " << *UseMI << '\n');
|
|
|
|
// Some constant folding cases change the same immediate's use to a new
|
|
// instruction, e.g. and x, 0 -> 0. Make sure we re-visit the user
|
|
// again. The same constant folded instruction could also have a second
|
|
// use operand.
|
|
NextUse = MRI->use_begin(Dst.getReg());
|
|
FoldList.clear();
|
|
continue;
|
|
}
|
|
|
|
// Try to fold any inline immediate uses, and then only fold other
|
|
// constants if they have one use.
|
|
//
|
|
// The legality of the inline immediate must be checked based on the use
|
|
// operand, not the defining instruction, because 32-bit instructions
|
|
// with 32-bit inline immediate sources may be used to materialize
|
|
// constants used in 16-bit operands.
|
|
//
|
|
// e.g. it is unsafe to fold:
|
|
// s_mov_b32 s0, 1.0 // materializes 0x3f800000
|
|
// v_add_f16 v0, v1, s0 // 1.0 f16 inline immediate sees 0x00003c00
|
|
|
|
// Folding immediates with more than one use will increase program size.
|
|
// FIXME: This will also reduce register usage, which may be better
|
|
// in some cases. A better heuristic is needed.
|
|
if (isInlineConstantIfFolded(TII, *UseMI, OpNo, OpToFold)) {
|
|
foldOperand(OpToFold, UseMI, OpNo, FoldList, CopiesToReplace);
|
|
} else if (frameIndexMayFold(TII, *UseMI, OpNo, OpToFold)) {
|
|
foldOperand(OpToFold, UseMI, OpNo, FoldList,
|
|
CopiesToReplace);
|
|
} else {
|
|
if (++NumLiteralUses == 1) {
|
|
NonInlineUse = &*Use;
|
|
NonInlineUseOpNo = OpNo;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (NumLiteralUses == 1) {
|
|
MachineInstr *UseMI = NonInlineUse->getParent();
|
|
foldOperand(OpToFold, UseMI, NonInlineUseOpNo, FoldList, CopiesToReplace);
|
|
}
|
|
} else {
|
|
// Folding register.
|
|
SmallVector <MachineRegisterInfo::use_iterator, 4> UsesToProcess;
|
|
for (MachineRegisterInfo::use_iterator
|
|
Use = MRI->use_begin(Dst.getReg()), E = MRI->use_end();
|
|
Use != E; ++Use) {
|
|
UsesToProcess.push_back(Use);
|
|
}
|
|
for (auto U : UsesToProcess) {
|
|
MachineInstr *UseMI = U->getParent();
|
|
|
|
foldOperand(OpToFold, UseMI, U.getOperandNo(),
|
|
FoldList, CopiesToReplace);
|
|
}
|
|
}
|
|
|
|
MachineFunction *MF = MI.getParent()->getParent();
|
|
// Make sure we add EXEC uses to any new v_mov instructions created.
|
|
for (MachineInstr *Copy : CopiesToReplace)
|
|
Copy->addImplicitDefUseOperands(*MF);
|
|
|
|
for (FoldCandidate &Fold : FoldList) {
|
|
assert(!Fold.isReg() || Fold.OpToFold);
|
|
if (Fold.isReg() && Register::isVirtualRegister(Fold.OpToFold->getReg())) {
|
|
Register Reg = Fold.OpToFold->getReg();
|
|
MachineInstr *DefMI = Fold.OpToFold->getParent();
|
|
if (DefMI->readsRegister(AMDGPU::EXEC, TRI) &&
|
|
execMayBeModifiedBeforeUse(*MRI, Reg, *DefMI, *Fold.UseMI))
|
|
continue;
|
|
}
|
|
if (updateOperand(Fold, *TII, *TRI, *ST)) {
|
|
// Clear kill flags.
|
|
if (Fold.isReg()) {
|
|
assert(Fold.OpToFold && Fold.OpToFold->isReg());
|
|
// FIXME: Probably shouldn't bother trying to fold if not an
|
|
// SGPR. PeepholeOptimizer can eliminate redundant VGPR->VGPR
|
|
// copies.
|
|
MRI->clearKillFlags(Fold.OpToFold->getReg());
|
|
}
|
|
LLVM_DEBUG(dbgs() << "Folded source from " << MI << " into OpNo "
|
|
<< static_cast<int>(Fold.UseOpNo) << " of "
|
|
<< *Fold.UseMI << '\n');
|
|
tryFoldInst(TII, Fold.UseMI);
|
|
} else if (Fold.isCommuted()) {
|
|
// Restoring instruction's original operand order if fold has failed.
|
|
TII->commuteInstruction(*Fold.UseMI, false);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Clamp patterns are canonically selected to v_max_* instructions, so only
|
|
// handle them.
|
|
const MachineOperand *SIFoldOperands::isClamp(const MachineInstr &MI) const {
|
|
unsigned Op = MI.getOpcode();
|
|
switch (Op) {
|
|
case AMDGPU::V_MAX_F32_e64:
|
|
case AMDGPU::V_MAX_F16_e64:
|
|
case AMDGPU::V_MAX_F64:
|
|
case AMDGPU::V_PK_MAX_F16: {
|
|
if (!TII->getNamedOperand(MI, AMDGPU::OpName::clamp)->getImm())
|
|
return nullptr;
|
|
|
|
// Make sure sources are identical.
|
|
const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
|
|
const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
|
|
if (!Src0->isReg() || !Src1->isReg() ||
|
|
Src0->getReg() != Src1->getReg() ||
|
|
Src0->getSubReg() != Src1->getSubReg() ||
|
|
Src0->getSubReg() != AMDGPU::NoSubRegister)
|
|
return nullptr;
|
|
|
|
// Can't fold up if we have modifiers.
|
|
if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
|
|
return nullptr;
|
|
|
|
unsigned Src0Mods
|
|
= TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)->getImm();
|
|
unsigned Src1Mods
|
|
= TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers)->getImm();
|
|
|
|
// Having a 0 op_sel_hi would require swizzling the output in the source
|
|
// instruction, which we can't do.
|
|
unsigned UnsetMods = (Op == AMDGPU::V_PK_MAX_F16) ? SISrcMods::OP_SEL_1
|
|
: 0u;
|
|
if (Src0Mods != UnsetMods && Src1Mods != UnsetMods)
|
|
return nullptr;
|
|
return Src0;
|
|
}
|
|
default:
|
|
return nullptr;
|
|
}
|
|
}
|
|
|
|
// We obviously have multiple uses in a clamp since the register is used twice
|
|
// in the same instruction.
|
|
static bool hasOneNonDBGUseInst(const MachineRegisterInfo &MRI, unsigned Reg) {
|
|
int Count = 0;
|
|
for (auto I = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end();
|
|
I != E; ++I) {
|
|
if (++Count > 1)
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
// FIXME: Clamp for v_mad_mixhi_f16 handled during isel.
|
|
bool SIFoldOperands::tryFoldClamp(MachineInstr &MI) {
|
|
const MachineOperand *ClampSrc = isClamp(MI);
|
|
if (!ClampSrc || !hasOneNonDBGUseInst(*MRI, ClampSrc->getReg()))
|
|
return false;
|
|
|
|
MachineInstr *Def = MRI->getVRegDef(ClampSrc->getReg());
|
|
|
|
// The type of clamp must be compatible.
|
|
if (TII->getClampMask(*Def) != TII->getClampMask(MI))
|
|
return false;
|
|
|
|
MachineOperand *DefClamp = TII->getNamedOperand(*Def, AMDGPU::OpName::clamp);
|
|
if (!DefClamp)
|
|
return false;
|
|
|
|
LLVM_DEBUG(dbgs() << "Folding clamp " << *DefClamp << " into " << *Def
|
|
<< '\n');
|
|
|
|
// Clamp is applied after omod, so it is OK if omod is set.
|
|
DefClamp->setImm(1);
|
|
MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
static int getOModValue(unsigned Opc, int64_t Val) {
|
|
switch (Opc) {
|
|
case AMDGPU::V_MUL_F32_e64: {
|
|
switch (static_cast<uint32_t>(Val)) {
|
|
case 0x3f000000: // 0.5
|
|
return SIOutMods::DIV2;
|
|
case 0x40000000: // 2.0
|
|
return SIOutMods::MUL2;
|
|
case 0x40800000: // 4.0
|
|
return SIOutMods::MUL4;
|
|
default:
|
|
return SIOutMods::NONE;
|
|
}
|
|
}
|
|
case AMDGPU::V_MUL_F16_e64: {
|
|
switch (static_cast<uint16_t>(Val)) {
|
|
case 0x3800: // 0.5
|
|
return SIOutMods::DIV2;
|
|
case 0x4000: // 2.0
|
|
return SIOutMods::MUL2;
|
|
case 0x4400: // 4.0
|
|
return SIOutMods::MUL4;
|
|
default:
|
|
return SIOutMods::NONE;
|
|
}
|
|
}
|
|
default:
|
|
llvm_unreachable("invalid mul opcode");
|
|
}
|
|
}
|
|
|
|
// FIXME: Does this really not support denormals with f16?
|
|
// FIXME: Does this need to check IEEE mode bit? SNaNs are generally not
|
|
// handled, so will anything other than that break?
|
|
std::pair<const MachineOperand *, int>
|
|
SIFoldOperands::isOMod(const MachineInstr &MI) const {
|
|
unsigned Op = MI.getOpcode();
|
|
switch (Op) {
|
|
case AMDGPU::V_MUL_F32_e64:
|
|
case AMDGPU::V_MUL_F16_e64: {
|
|
// If output denormals are enabled, omod is ignored.
|
|
if ((Op == AMDGPU::V_MUL_F32_e64 && MFI->getMode().FP32Denormals) ||
|
|
(Op == AMDGPU::V_MUL_F16_e64 && MFI->getMode().FP64FP16Denormals))
|
|
return std::make_pair(nullptr, SIOutMods::NONE);
|
|
|
|
const MachineOperand *RegOp = nullptr;
|
|
const MachineOperand *ImmOp = nullptr;
|
|
const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
|
|
const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
|
|
if (Src0->isImm()) {
|
|
ImmOp = Src0;
|
|
RegOp = Src1;
|
|
} else if (Src1->isImm()) {
|
|
ImmOp = Src1;
|
|
RegOp = Src0;
|
|
} else
|
|
return std::make_pair(nullptr, SIOutMods::NONE);
|
|
|
|
int OMod = getOModValue(Op, ImmOp->getImm());
|
|
if (OMod == SIOutMods::NONE ||
|
|
TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) ||
|
|
TII->hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) ||
|
|
TII->hasModifiersSet(MI, AMDGPU::OpName::omod) ||
|
|
TII->hasModifiersSet(MI, AMDGPU::OpName::clamp))
|
|
return std::make_pair(nullptr, SIOutMods::NONE);
|
|
|
|
return std::make_pair(RegOp, OMod);
|
|
}
|
|
case AMDGPU::V_ADD_F32_e64:
|
|
case AMDGPU::V_ADD_F16_e64: {
|
|
// If output denormals are enabled, omod is ignored.
|
|
if ((Op == AMDGPU::V_ADD_F32_e64 && MFI->getMode().FP32Denormals) ||
|
|
(Op == AMDGPU::V_ADD_F16_e64 && MFI->getMode().FP64FP16Denormals))
|
|
return std::make_pair(nullptr, SIOutMods::NONE);
|
|
|
|
// Look through the DAGCombiner canonicalization fmul x, 2 -> fadd x, x
|
|
const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
|
|
const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
|
|
|
|
if (Src0->isReg() && Src1->isReg() && Src0->getReg() == Src1->getReg() &&
|
|
Src0->getSubReg() == Src1->getSubReg() &&
|
|
!TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) &&
|
|
!TII->hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) &&
|
|
!TII->hasModifiersSet(MI, AMDGPU::OpName::clamp) &&
|
|
!TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
|
|
return std::make_pair(Src0, SIOutMods::MUL2);
|
|
|
|
return std::make_pair(nullptr, SIOutMods::NONE);
|
|
}
|
|
default:
|
|
return std::make_pair(nullptr, SIOutMods::NONE);
|
|
}
|
|
}
|
|
|
|
// FIXME: Does this need to check IEEE bit on function?
|
|
bool SIFoldOperands::tryFoldOMod(MachineInstr &MI) {
|
|
const MachineOperand *RegOp;
|
|
int OMod;
|
|
std::tie(RegOp, OMod) = isOMod(MI);
|
|
if (OMod == SIOutMods::NONE || !RegOp->isReg() ||
|
|
RegOp->getSubReg() != AMDGPU::NoSubRegister ||
|
|
!hasOneNonDBGUseInst(*MRI, RegOp->getReg()))
|
|
return false;
|
|
|
|
MachineInstr *Def = MRI->getVRegDef(RegOp->getReg());
|
|
MachineOperand *DefOMod = TII->getNamedOperand(*Def, AMDGPU::OpName::omod);
|
|
if (!DefOMod || DefOMod->getImm() != SIOutMods::NONE)
|
|
return false;
|
|
|
|
// Clamp is applied after omod. If the source already has clamp set, don't
|
|
// fold it.
|
|
if (TII->hasModifiersSet(*Def, AMDGPU::OpName::clamp))
|
|
return false;
|
|
|
|
LLVM_DEBUG(dbgs() << "Folding omod " << MI << " into " << *Def << '\n');
|
|
|
|
DefOMod->setImm(OMod);
|
|
MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
|
|
if (skipFunction(MF.getFunction()))
|
|
return false;
|
|
|
|
MRI = &MF.getRegInfo();
|
|
ST = &MF.getSubtarget<GCNSubtarget>();
|
|
TII = ST->getInstrInfo();
|
|
TRI = &TII->getRegisterInfo();
|
|
MFI = MF.getInfo<SIMachineFunctionInfo>();
|
|
|
|
// omod is ignored by hardware if IEEE bit is enabled. omod also does not
|
|
// correctly handle signed zeros.
|
|
//
|
|
// FIXME: Also need to check strictfp
|
|
bool IsIEEEMode = MFI->getMode().IEEE;
|
|
bool HasNSZ = MFI->hasNoSignedZerosFPMath();
|
|
|
|
for (MachineBasicBlock *MBB : depth_first(&MF)) {
|
|
MachineBasicBlock::iterator I, Next;
|
|
|
|
MachineOperand *CurrentKnownM0Val = nullptr;
|
|
for (I = MBB->begin(); I != MBB->end(); I = Next) {
|
|
Next = std::next(I);
|
|
MachineInstr &MI = *I;
|
|
|
|
tryFoldInst(TII, &MI);
|
|
|
|
if (!TII->isFoldableCopy(MI)) {
|
|
// Saw an unknown clobber of m0, so we no longer know what it is.
|
|
if (CurrentKnownM0Val && MI.modifiesRegister(AMDGPU::M0, TRI))
|
|
CurrentKnownM0Val = nullptr;
|
|
|
|
// TODO: Omod might be OK if there is NSZ only on the source
|
|
// instruction, and not the omod multiply.
|
|
if (IsIEEEMode || (!HasNSZ && !MI.getFlag(MachineInstr::FmNsz)) ||
|
|
!tryFoldOMod(MI))
|
|
tryFoldClamp(MI);
|
|
|
|
continue;
|
|
}
|
|
|
|
// Specially track simple redefs of m0 to the same value in a block, so we
|
|
// can erase the later ones.
|
|
if (MI.getOperand(0).getReg() == AMDGPU::M0) {
|
|
MachineOperand &NewM0Val = MI.getOperand(1);
|
|
if (CurrentKnownM0Val && CurrentKnownM0Val->isIdenticalTo(NewM0Val)) {
|
|
MI.eraseFromParent();
|
|
continue;
|
|
}
|
|
|
|
// We aren't tracking other physical registers
|
|
CurrentKnownM0Val = (NewM0Val.isReg() && NewM0Val.getReg().isPhysical()) ?
|
|
nullptr : &NewM0Val;
|
|
continue;
|
|
}
|
|
|
|
MachineOperand &OpToFold = MI.getOperand(1);
|
|
bool FoldingImm =
|
|
OpToFold.isImm() || OpToFold.isFI() || OpToFold.isGlobal();
|
|
|
|
// FIXME: We could also be folding things like TargetIndexes.
|
|
if (!FoldingImm && !OpToFold.isReg())
|
|
continue;
|
|
|
|
if (OpToFold.isReg() && !Register::isVirtualRegister(OpToFold.getReg()))
|
|
continue;
|
|
|
|
// Prevent folding operands backwards in the function. For example,
|
|
// the COPY opcode must not be replaced by 1 in this example:
|
|
//
|
|
// %3 = COPY %vgpr0; VGPR_32:%3
|
|
// ...
|
|
// %vgpr0 = V_MOV_B32_e32 1, implicit %exec
|
|
MachineOperand &Dst = MI.getOperand(0);
|
|
if (Dst.isReg() && !Register::isVirtualRegister(Dst.getReg()))
|
|
continue;
|
|
|
|
foldInstOperand(MI, OpToFold);
|
|
}
|
|
}
|
|
return true;
|
|
}
|