forked from OSchip/llvm-project
195 lines
6.6 KiB
LLVM
195 lines
6.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa < %s | FileCheck %s
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; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -passes='require<domtree>,loop(simplify-cfg)' -verify-loop-info -verify-dom-info -verify-loop-lcssa < %s | FileCheck %s
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; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -enable-mssa-loop-dependency=true -verify-memoryssa -verify-loop-info -verify-dom-info -verify-loop-lcssa < %s | FileCheck %s
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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define void @c() {
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; CHECK-LABEL: @c(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[D:%.*]]
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; CHECK: d.loopexit:
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; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi i32 [ [[TMP1:%.*]], [[FOR_COND:%.*]] ]
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; CHECK-NEXT: br label [[D]]
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; CHECK: d:
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; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[DOTLCSSA]], [[D_LOOPEXIT:%.*]] ]
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; CHECK-NEXT: br label [[FOR_COND]]
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; CHECK: for.cond:
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; CHECK-NEXT: [[TMP1]] = phi i32 [ [[TMP0]], [[D]] ], [ 0, [[IF_END:%.*]] ]
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; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp eq i32 [[TMP1]], 0
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; CHECK-NEXT: br i1 [[TOBOOL2]], label [[IF_END]], label [[D_LOOPEXIT]]
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; CHECK: if.end:
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; CHECK-NEXT: br label [[FOR_COND]]
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;
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entry:
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br label %d
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d.loopexit: ; preds = %if.end.7, %for.body
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%.lcssa = phi i32 [ %1, %for.body ], [ 0, %if.end.7 ]
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br label %d
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d: ; preds = %d.loopexit, %entry
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%0 = phi i32 [ undef, %entry ], [ %.lcssa, %d.loopexit ]
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br label %for.cond
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for.cond: ; preds = %if.end.8, %d
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%1 = phi i32 [ %0, %d ], [ 0, %if.end.8 ]
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br label %for.body
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for.body: ; preds = %for.cond
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%tobool2 = icmp eq i32 %1, 0
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br i1 %tobool2, label %if.end, label %d.loopexit
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if.end: ; preds = %for.body
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br label %if.end.7
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if.end.7: ; preds = %if.end
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br i1 true, label %if.end.8, label %d.loopexit
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if.end.8: ; preds = %if.end.7
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br label %for.cond
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}
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define void @test_01() {
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; CHECK-LABEL: @test_01(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_COND:%.*]]
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; CHECK: for.cond.loopexit:
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; CHECK-NEXT: br label [[FOR_COND]]
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; CHECK: for.cond:
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; CHECK-NEXT: [[INC41_LCSSA3:%.*]] = phi i16 [ undef, [[FOR_COND_LOOPEXIT:%.*]] ], [ undef, [[ENTRY:%.*]] ]
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; CHECK-NEXT: switch i32 0, label [[FOR_COND_SPLIT:%.*]] [
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; CHECK-NEXT: i32 1, label [[FOR_COND_LOOPEXIT]]
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; CHECK-NEXT: ]
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; CHECK: for.cond.split:
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; CHECK-NEXT: [[INC41_LCSSA3_LCSSA:%.*]] = phi i16 [ [[INC41_LCSSA3]], [[FOR_COND]] ]
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; CHECK-NEXT: br label [[WHILE_COND:%.*]]
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; CHECK: while.cond:
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; CHECK-NEXT: [[INC41:%.*]] = phi i16 [ [[INC4:%.*]], [[WHILE_COND]] ], [ [[INC41_LCSSA3_LCSSA]], [[FOR_COND_SPLIT]] ]
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; CHECK-NEXT: [[INC4]] = add nsw i16 [[INC41]], 1
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; CHECK-NEXT: br label [[WHILE_COND]]
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;
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entry:
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br label %for.cond
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for.cond.loopexit: ; preds = %while.cond
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%inc41.lcssa = phi i16 [ %inc41, %while.cond ]
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br label %for.cond
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for.cond: ; preds = %for.cond.loopexit, %entry
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%inc41.lcssa3 = phi i16 [ %inc41.lcssa, %for.cond.loopexit ], [ undef, %entry ]
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br label %while.cond
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while.cond: ; preds = %while.body, %for.cond
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%inc41 = phi i16 [ %inc4, %while.body ], [ %inc41.lcssa3, %for.cond ]
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br i1 true, label %while.body, label %for.cond.loopexit
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while.body: ; preds = %while.cond
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%inc4 = add nsw i16 %inc41, 1
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br label %while.cond
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}
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define void @bar() {
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; CHECK-LABEL: @bar(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: switch i32 0, label [[BB_SPLIT:%.*]] [
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; CHECK-NEXT: i32 1, label [[BB10:%.*]]
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; CHECK-NEXT: ]
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; CHECK: bb.split:
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; CHECK-NEXT: br label [[BB1:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ [[TMP7:%.*]], [[BB6:%.*]] ], [ undef, [[BB_SPLIT]] ]
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; CHECK-NEXT: switch i32 undef, label [[BB5:%.*]] [
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; CHECK-NEXT: i32 0, label [[BB6]]
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; CHECK-NEXT: i32 1, label [[BB8:%.*]]
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; CHECK-NEXT: ]
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; CHECK: bb5:
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; CHECK-NEXT: ret void
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; CHECK: bb6:
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; CHECK-NEXT: [[TMP7]] = add i32 undef, 123
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; CHECK-NEXT: br label [[BB1]]
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; CHECK: bb8:
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; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP]], [[BB1]] ]
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; CHECK-NEXT: [[USE:%.*]] = add i32 [[TMP9]], 1
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; CHECK-NEXT: ret void
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; CHECK: bb10:
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; CHECK-NEXT: ret void
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;
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bb:
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br label %bb1
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bb1: ; preds = %bb6, %bb
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%tmp = phi i32 [ %tmp7, %bb6 ], [ undef, %bb ]
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br i1 false, label %bb2, label %bb4
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bb2: ; preds = %bb1
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switch i32 undef, label %bb10 [
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i32 0, label %bb3
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i32 1, label %bb8
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]
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bb3: ; preds = %bb2
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br label %bb6
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bb4: ; preds = %bb1
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switch i32 undef, label %bb5 [
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i32 0, label %bb6
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i32 1, label %bb8
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]
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bb5: ; preds = %bb4
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ret void
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bb6: ; preds = %bb4, %bb3
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%tmp7 = add i32 undef, 123
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br label %bb1
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bb8: ; preds = %bb4, %bb2
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%tmp9 = phi i32 [ %tmp, %bb2 ], [ %tmp, %bb4 ]
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%use = add i32 %tmp9, 1
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ret void
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bb10: ; preds = %bb2
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ret void
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}
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define void @memlcssa() {
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; CHECK-LABEL: @memlcssa(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i32 0, label [[ENTRY_SPLIT:%.*]] [
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; CHECK-NEXT: i32 1, label [[DEFAULT_BB:%.*]]
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; CHECK-NEXT: ]
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; CHECK: entry.split:
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: call void @foo()
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; CHECK-NEXT: br label [[FOR_BODY]]
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; CHECK: default.bb:
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; CHECK-NEXT: unreachable
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;
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entry:
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br label %for.body
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for.body: ; preds = %exit, %entry
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br label %switch.bb
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switch.bb: ; preds = %for.body
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switch i2 1, label %default.bb [
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i2 1, label %case.bb
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]
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case.bb: ; preds = %switch
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br label %exit
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default.bb: ; preds = %switch
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unreachable
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exit: ; preds = %case.bb
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call void @foo()
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br label %for.body
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}
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declare void @foo()
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