forked from OSchip/llvm-project
120 lines
3.8 KiB
C++
120 lines
3.8 KiB
C++
//===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that XCore uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef XCOREISELLOWERING_H
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#define XCOREISELLOWERING_H
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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#include "XCore.h"
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namespace llvm {
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// Forward delcarations
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class XCoreSubtarget;
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class XCoreTargetMachine;
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namespace XCoreISD {
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enum NodeType {
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// Start the numbering where the builtin ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+XCore::INSTRUCTION_LIST_END,
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// Branch and link (call)
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BL,
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// pc relative address
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PCRelativeWrapper,
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// dp relative address
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DPRelativeWrapper,
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// cp relative address
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CPRelativeWrapper,
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// Store word to stack
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STWSP,
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// Corresponds to retsp instruction
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RETSP,
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// Corresponds to LADD instruction
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LADD,
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// Corresponds to LSUB instruction
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LSUB
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};
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}
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//===--------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===--------------------------------------------------------------------===//
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class XCoreTargetLowering : public TargetLowering
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{
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public:
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explicit XCoreTargetLowering(XCoreTargetMachine &TM);
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/// LowerOperation - Provide custom lowering hooks for some operations.
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
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virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG);
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/// getTargetNodeName - This method returns the name of a target specific
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// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB);
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virtual bool isLegalAddressingMode(const AddrMode &AM,
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const Type *Ty) const;
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private:
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const XCoreTargetMachine &TM;
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const XCoreSubtarget &Subtarget;
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// Lower Operand helpers
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SDValue LowerCCCArguments(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC);
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SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode*TheCall,
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unsigned CallingConv, SelectionDAG &DAG);
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SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
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SDValue getGlobalAddressWrapper(SDValue GA, GlobalValue *GV,
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SelectionDAG &DAG);
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// Lower Operand specifics
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SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
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SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG);
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
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// Inline asm support
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const;
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// Expand specifics
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SDNode *ExpandADDSUB(SDNode *Op, SelectionDAG &DAG);
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};
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}
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#endif // XCOREISELLOWERING_H
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