..
AsmParser
[AArch64][AsmParser] NFC: Remove unused ExtendOp struct
2021-04-20 13:45:09 +00:00
Disassembler
[AArch64] Adding the v8.7-A LD64B/ST64B Accelerator extension
2020-12-17 13:46:23 +00:00
GISel
[AArch64][GlobalISel] Use a single MachineIRBuilder for most of isel. NFC.
2021-04-30 14:49:41 -07:00
MCTargetDesc
[AArch64] [COFF] Properly produce cross-section relative relocations
2021-04-14 12:31:26 +03:00
TargetInfo
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
Utils
[ARM][AArch64] Adding basic support for the v8.7-A architecture
2020-12-17 13:45:08 +00:00
AArch64.h
[AArch64] Homogeneous Prolog and Epilog Size Optimization
2021-02-02 14:57:26 -08:00
AArch64.td
[AArch64] Enable UseAA globally in the AArch64 backend
2021-04-24 17:51:50 +01:00
AArch64A53Fix835769.cpp
…
AArch64A57FPLoadBalancing.cpp
…
AArch64AdvSIMDScalarPass.cpp
[AArch64] Update a code comment incorrectly referring to zero_reg. NFC
2020-08-20 14:36:59 +02:00
AArch64AsmPrinter.cpp
[NFC] Refactor how CFI section types are represented in AsmPrinter
2021-04-28 09:04:04 +05:30
AArch64BranchTargets.cpp
[AArch64] Fix for BTI landing pad insertion with PAC-RET+bkey.
2021-04-23 10:07:25 +02:00
AArch64CallingConvention.cpp
[clang][AArch64] Correctly align HFA arguments when passed on the stack
2021-04-15 22:58:14 +01:00
AArch64CallingConvention.h
…
AArch64CallingConvention.td
[AArch64] Fix windows vararg functions with floats in the fixed args
2021-04-15 11:02:14 +03:00
AArch64CleanupLocalDynamicTLSPass.cpp
…
AArch64CollectLOH.cpp
[AArch64] Fix emitting an AdrpAddLdr LOH when there's a potential clobber of the
2021-03-01 13:52:57 -08:00
AArch64Combine.td
[AArch64][GlobalISel] Simplify out of range rotate amount.
2021-04-29 14:05:58 -07:00
AArch64CompressJumpTables.cpp
[AArch64] Don't try to compress jump tables if there are any inline asm instructions.
2020-12-10 12:20:02 -08:00
AArch64CondBrTuning.cpp
…
AArch64ConditionOptimizer.cpp
…
AArch64ConditionalCompares.cpp
…
AArch64DeadRegisterDefinitionsPass.cpp
…
AArch64ExpandImm.cpp
…
AArch64ExpandImm.h
…
AArch64ExpandPseudoInsts.cpp
[AArch64] Add implicit uses for operands when expanding BLR_RVMARKER.
2021-03-03 21:56:05 +00:00
AArch64FalkorHWPFFix.cpp
Small fixes for "[LoopInfo] empty() -> isInnermost(), add isOutermost()"
2020-09-22 23:59:34 +03:00
AArch64FastISel.cpp
Revert "Allow invokable sub-classes of IntrinsicInst"
2021-04-20 15:38:38 -07:00
AArch64FrameLowering.cpp
[NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions
2021-03-30 17:31:39 +01:00
AArch64FrameLowering.h
[AArch64] Homogeneous Prolog and Epilog Size Optimization
2021-02-02 14:57:26 -08:00
AArch64GenRegisterBankInfo.def
…
AArch64ISelDAGToDAG.cpp
[Aarch64] handle "o" inline asm memory constraints
2021-04-15 23:36:21 -07:00
AArch64ISelLowering.cpp
[AArch64] Prevent spilling between ldxr/stxr pairs
2021-05-01 17:17:05 +02:00
AArch64ISelLowering.h
[AArch64][SVE] Lower index_vector to step_vector
2021-04-30 19:04:39 +08:00
AArch64InstrAtomics.td
…
AArch64InstrFormats.td
[AArch64] Implement __rndr, __rndrrs intrinsics
2021-03-15 17:51:48 +00:00
AArch64InstrGISel.td
AArch64: support atomics in GISel
2021-04-26 14:38:06 +01:00
AArch64InstrInfo.cpp
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR.
2021-04-30 17:29:58 +01:00
AArch64InstrInfo.h
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR.
2021-04-30 17:29:58 +01:00
AArch64InstrInfo.td
AArch64: support atomics in GISel
2021-04-26 14:38:06 +01:00
AArch64LoadStoreOptimizer.cpp
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR.
2021-04-30 17:29:58 +01:00
AArch64LowerHomogeneousPrologEpilog.cpp
AArch64LowerHomogeneousPrologEpilog.cpp - fix Wdocumentation warning. NFCI.
2021-02-05 11:34:43 +00:00
AArch64MCInstLower.cpp
[AArch64] [Windows] Properly add :lo12: reloc specifiers when generating assembly
2021-01-12 23:56:03 +02:00
AArch64MCInstLower.h
…
AArch64MachineFunctionInfo.cpp
[AArch64] PAC/BTI code generation for LLVM generated functions
2020-09-25 11:47:14 +01:00
AArch64MachineFunctionInfo.h
Revert "[AArch64][SVE] Allow accesses to SVE stack objects to use frame pointer"
2021-03-11 13:32:35 +00:00
AArch64MacroFusion.cpp
[AArch64] Add Cortex CPU subtarget features for instruction fusion.
2021-01-25 09:11:29 +00:00
AArch64MacroFusion.h
[llvm] Add missing header guards (NFC)
2021-01-30 09:53:42 -08:00
AArch64PBQPRegAlloc.cpp
…
AArch64PBQPRegAlloc.h
…
AArch64PerfectShuffle.h
…
AArch64PfmCounters.td
…
AArch64PromoteConstant.cpp
…
AArch64RedundantCopyElimination.cpp
[AArch64] Fix Copy Elemination for negative values
2020-12-18 13:30:46 +00:00
AArch64RegisterBanks.td
…
AArch64RegisterInfo.cpp
[NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions
2021-03-30 17:31:39 +01:00
AArch64RegisterInfo.h
Change materializeFrameBaseRegister() to return register
2021-01-22 15:51:06 -08:00
AArch64RegisterInfo.td
[AArch64] Add a GPR64x8 register class
2020-12-17 13:45:46 +00:00
AArch64SIMDInstrOpt.cpp
[AArch64] reuse another map iterator. NFC
2020-09-28 11:30:21 -07:00
AArch64SLSHardening.cpp
…
AArch64SVEInstrInfo.td
[AArch64][SVE] Lower index_vector to step_vector
2021-04-30 19:04:39 +08:00
AArch64SchedA53.td
…
AArch64SchedA55.td
[MCA] Disable RCU for InOrderIssueStage
2021-03-24 13:54:04 +03:00
AArch64SchedA57.td
[AARCH64] Improve accumulator forwarding for Cortex-A57 model
2021-01-04 10:58:43 +00:00
AArch64SchedA57WriteRes.td
[AARCH64] Improve accumulator forwarding for Cortex-A57 model
2021-01-04 10:58:43 +00:00
AArch64SchedA64FX.td
[AArch64] Add Fujitsu A64FX scheduling model
2021-01-15 17:14:04 +09:00
AArch64SchedCyclone.td
…
AArch64SchedExynosM3.td
…
AArch64SchedExynosM4.td
…
AArch64SchedExynosM5.td
…
AArch64SchedFalkor.td
…
AArch64SchedFalkorDetails.td
…
AArch64SchedKryo.td
…
AArch64SchedKryoDetails.td
…
AArch64SchedPredExynos.td
…
AArch64SchedPredicates.td
…
AArch64SchedTSV110.td
[AArch64] Add pipeline model for HiSilicon's TSV110
2020-11-07 01:23:00 +03:00
AArch64SchedThunderX.td
…
AArch64SchedThunderX2T99.td
…
AArch64SchedThunderX3T110.td
…
AArch64Schedule.td
…
AArch64SelectionDAGInfo.cpp
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
2021-02-18 16:55:16 +00:00
AArch64SelectionDAGInfo.h
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
2021-02-18 16:55:16 +00:00
AArch64SpeculationHardening.cpp
…
AArch64StackTagging.cpp
Reapply "[DebugInfo] Handle multiple variable location operands in IR"
2021-03-17 16:45:25 +00:00
AArch64StackTaggingPreRA.cpp
[MTE] Pin the tagged base pointer to one of the stack slots.
2020-10-15 12:50:16 -07:00
AArch64StorePairSuppress.cpp
…
AArch64Subtarget.cpp
[AArch64] Sets the preferred function alignment for Cortex-A53/A55.
2021-05-03 00:00:10 +01:00
AArch64Subtarget.h
[AArch64] Enable UseAA globally in the AArch64 backend
2021-04-24 17:51:50 +01:00
AArch64SystemOperands.td
[AArch64] Add +pauth archictecture option, allowing the v8.3a pointer authentication extension.
2021-01-08 13:21:11 +00:00
AArch64TargetMachine.cpp
[AArch64][GlobalISel] Enable use of the optsize predicate in the selector.
2021-03-02 12:55:51 -08:00
AArch64TargetMachine.h
…
AArch64TargetObjectFile.cpp
…
AArch64TargetObjectFile.h
…
AArch64TargetTransformInfo.cpp
[TTI] NFC: Change getTypeLegalizationCost to return InstructionCost.
2021-04-30 22:51:51 +03:00
AArch64TargetTransformInfo.h
[AArch64] Add AArch64TTIImpl::getMaskedMemoryOpCost function
2021-04-26 11:00:03 +01:00
CMakeLists.txt
[AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP
2021-03-08 13:01:10 -08:00
SVEInstrFormats.td
[AArch64][SVE] Lower index_vector to step_vector
2021-04-30 19:04:39 +08:00
SVEIntrinsicOpts.cpp
[AArch64][SVE] Remove unused function missed from D101302
2021-04-30 16:57:09 +01:00
