forked from OSchip/llvm-project
25 lines
707 B
TableGen
25 lines
707 B
TableGen
//===- ARC.td - Describe the ARC Target Machine ------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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include "ARCRegisterInfo.td"
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include "ARCInstrInfo.td"
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include "ARCCallingConv.td"
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def ARCInstrInfo : InstrInfo;
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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def ARC : Target {
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let InstructionSet = ARCInstrInfo;
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}
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