llvm-project/llvm/test/CodeGen
David Green 15b5d1a5bf [ARM] Transfer memory operands for VLDn
We create MMO's for the VLDn/VSTn intrinsics in ARMTargetLowering::
getTgtMemIntrinsic, but they do not currently make it ll the way through
ISel.  This changes that in the various places it needs changing, making
sure that the MMO is propagate through to the final instruction. This
can help in scheduling, not treating the VLD2/VST2 as a scheduling
barrier.

Differential Revision: https://reviews.llvm.org/D101096
2021-05-03 00:04:21 +01:00
..
AArch64 [AArch64] Sets the preferred function alignment for Cortex-A53/A55. 2021-05-03 00:00:10 +01:00
AMDGPU [AMDGPU] Remove set_gpr_idx instructions in conditional blocks 2021-04-30 22:15:45 +01:00
ARC
ARM Revert "[VP,Integer,#2] ExpandVectorPredication pass" 2021-04-30 17:02:28 -07:00
AVR
BPF BPF: generate BTF info for LD_imm64 loaded function pointer 2021-04-26 17:23:36 -07:00
Generic Revert "[VP,Integer,#2] ExpandVectorPredication pass" 2021-04-30 17:02:28 -07:00
Hexagon [Hexagon] Improve lowering of returns of i1 2021-04-22 16:47:52 -05:00
Inputs
Lanai
M68k [DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling 2021-03-19 16:02:31 +00:00
MIR [AMDGPU] Set implicit arg attributes for indirect calls 2021-04-13 13:15:13 +00:00
MSP430
Mips [MIPS, test] Fix use of undef FileCheck var 2021-04-02 00:59:49 +01:00
NVPTX [NVPTX] Enable lowering of atomics on local memory 2021-04-26 20:12:12 -04:00
PowerPC [PowerPC] Add missing requirement to test case 2021-04-30 19:36:58 -05:00
RISCV [RISCV] Store SEW in RISCV vector pseudo instructions in log2 form. 2021-05-02 12:09:20 -07:00
SPARC
SystemZ
Thumb Support {S,U}REMEqFold before legalization 2021-04-01 01:35:41 +03:00
Thumb2 [ARM] Transfer memory operands for VLDn 2021-05-03 00:04:21 +01:00
VE
WebAssembly [WebAssembly] Error when wasm EH is used with Emscripten EH/SjLj 2021-04-27 16:07:53 -07:00
WinCFGuard
WinEH
X86 [X32][CET] Fix size and alignment of .note.gnu.property section 2021-05-01 22:17:04 +01:00
XCore