forked from OSchip/llvm-project
295 lines
8.7 KiB
LLVM
295 lines
8.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -aggressive-instcombine -S | FileCheck %s
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; PR37098 - https://bugs.llvm.org/show_bug.cgi?id=37098
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define i32 @anyset_two_bit_mask(i32 %x) {
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; CHECK-LABEL: @anyset_two_bit_mask(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 9
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
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; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
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; CHECK-NEXT: ret i32 [[TMP3]]
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;
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%s = lshr i32 %x, 3
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%o = or i32 %s, %x
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%r = and i32 %o, 1
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ret i32 %r
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}
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define <2 x i32> @anyset_two_bit_mask_uniform(<2 x i32> %x) {
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; CHECK-LABEL: @anyset_two_bit_mask_uniform(
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; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 9, i32 9>
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer
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; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[TMP3]]
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;
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%s = lshr <2 x i32> %x, <i32 3, i32 3>
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%o = or <2 x i32> %s, %x
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%r = and <2 x i32> %o, <i32 1, i32 1>
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ret <2 x i32> %r
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}
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define i32 @anyset_four_bit_mask(i32 %x) {
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; CHECK-LABEL: @anyset_four_bit_mask(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 297
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
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; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
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; CHECK-NEXT: ret i32 [[TMP3]]
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;
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%t1 = lshr i32 %x, 3
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%t2 = lshr i32 %x, 5
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%t3 = lshr i32 %x, 8
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%o1 = or i32 %t1, %x
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%o2 = or i32 %t2, %t3
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%o3 = or i32 %o1, %o2
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%r = and i32 %o3, 1
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ret i32 %r
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}
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define <2 x i32> @anyset_four_bit_mask_uniform(<2 x i32> %x) {
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; CHECK-LABEL: @anyset_four_bit_mask_uniform(
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; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 297, i32 297>
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer
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; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[TMP3]]
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;
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%t1 = lshr <2 x i32> %x, <i32 3, i32 3>
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%t2 = lshr <2 x i32> %x, <i32 5, i32 5>
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%t3 = lshr <2 x i32> %x, <i32 8, i32 8>
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%o1 = or <2 x i32> %t1, %x
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%o2 = or <2 x i32> %t2, %t3
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%o3 = or <2 x i32> %o1, %o2
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%r = and <2 x i32> %o3, <i32 1, i32 1>
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ret <2 x i32> %r
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}
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; We're not testing the LSB here, so all of the 'or' operands are shifts.
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define i32 @anyset_three_bit_mask_all_shifted_bits(i32 %x) {
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; CHECK-LABEL: @anyset_three_bit_mask_all_shifted_bits(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 296
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
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; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
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; CHECK-NEXT: ret i32 [[TMP3]]
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;
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%t1 = lshr i32 %x, 3
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%t2 = lshr i32 %x, 5
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%t3 = lshr i32 %x, 8
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%o2 = or i32 %t2, %t3
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%o3 = or i32 %t1, %o2
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%r = and i32 %o3, 1
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ret i32 %r
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}
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define <2 x i32> @anyset_three_bit_mask_all_shifted_bits_uniform(<2 x i32> %x) {
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; CHECK-LABEL: @anyset_three_bit_mask_all_shifted_bits_uniform(
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; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 296, i32 296>
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer
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; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[TMP3]]
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;
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%t1 = lshr <2 x i32> %x, <i32 3, i32 3>
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%t2 = lshr <2 x i32> %x, <i32 5, i32 5>
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%t3 = lshr <2 x i32> %x, <i32 8, i32 8>
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%o2 = or <2 x i32> %t2, %t3
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%o3 = or <2 x i32> %t1, %o2
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%r = and <2 x i32> %o3, <i32 1, i32 1>
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ret <2 x i32> %r
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}
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; Recognize the 'and' sibling pattern (all-bits-set). The 'and 1' may not be at the end.
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define i32 @allset_two_bit_mask(i32 %x) {
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; CHECK-LABEL: @allset_two_bit_mask(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 129
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 129
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; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
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; CHECK-NEXT: ret i32 [[TMP3]]
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;
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%s = lshr i32 %x, 7
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%o = and i32 %s, %x
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%r = and i32 %o, 1
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ret i32 %r
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}
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define <2 x i32> @allset_two_bit_mask_uniform(<2 x i32> %x) {
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; CHECK-LABEL: @allset_two_bit_mask_uniform(
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; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 129, i32 129>
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP1]], <i32 129, i32 129>
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; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[TMP3]]
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;
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%s = lshr <2 x i32> %x, <i32 7, i32 7>
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%o = and <2 x i32> %s, %x
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%r = and <2 x i32> %o, <i32 1, i32 1>
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ret <2 x i32> %r
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}
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define i64 @allset_four_bit_mask(i64 %x) {
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; CHECK-LABEL: @allset_four_bit_mask(
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; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[X:%.*]], 30
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 30
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; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
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; CHECK-NEXT: ret i64 [[TMP3]]
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;
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%t1 = lshr i64 %x, 1
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%t2 = lshr i64 %x, 2
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%t3 = lshr i64 %x, 3
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%t4 = lshr i64 %x, 4
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%a1 = and i64 %t4, 1
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%a2 = and i64 %t2, %a1
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%a3 = and i64 %a2, %t1
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%r = and i64 %a3, %t3
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ret i64 %r
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}
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declare void @use(i32)
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; negative test - extra use means the transform would increase instruction count
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define i32 @allset_two_bit_mask_multiuse(i32 %x) {
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; CHECK-LABEL: @allset_two_bit_mask_multiuse(
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; CHECK-NEXT: [[S:%.*]] = lshr i32 [[X:%.*]], 7
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; CHECK-NEXT: [[O:%.*]] = and i32 [[S]], [[X]]
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; CHECK-NEXT: [[R:%.*]] = and i32 [[O]], 1
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; CHECK-NEXT: call void @use(i32 [[O]])
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; CHECK-NEXT: ret i32 [[R]]
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;
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%s = lshr i32 %x, 7
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%o = and i32 %s, %x
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%r = and i32 %o, 1
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call void @use(i32 %o)
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ret i32 %r
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}
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; negative test - missing 'and 1' mask, so more than the low bit is used here
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define i8 @allset_three_bit_mask_no_and1(i8 %x) {
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; CHECK-LABEL: @allset_three_bit_mask_no_and1(
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; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[X:%.*]], 1
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; CHECK-NEXT: [[T2:%.*]] = lshr i8 [[X]], 2
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; CHECK-NEXT: [[T3:%.*]] = lshr i8 [[X]], 3
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; CHECK-NEXT: [[A2:%.*]] = and i8 [[T1]], [[T2]]
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; CHECK-NEXT: [[R:%.*]] = and i8 [[A2]], [[T3]]
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; CHECK-NEXT: ret i8 [[R]]
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;
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%t1 = lshr i8 %x, 1
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%t2 = lshr i8 %x, 2
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%t3 = lshr i8 %x, 3
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%a2 = and i8 %t1, %t2
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%r = and i8 %a2, %t3
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ret i8 %r
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}
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; This test demonstrates that the transform can be large. If the implementation
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; is slow or explosive (stack overflow due to recursion), it should be made efficient.
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define i64 @allset_40_bit_mask(i64 %x) {
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; CHECK-LABEL: @allset_40_bit_mask(
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; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[X:%.*]], 2199023255550
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2199023255550
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; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
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; CHECK-NEXT: ret i64 [[TMP3]]
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;
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%t1 = lshr i64 %x, 1
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%t2 = lshr i64 %x, 2
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%t3 = lshr i64 %x, 3
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%t4 = lshr i64 %x, 4
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%t5 = lshr i64 %x, 5
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%t6 = lshr i64 %x, 6
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%t7 = lshr i64 %x, 7
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%t8 = lshr i64 %x, 8
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%t9 = lshr i64 %x, 9
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%t10 = lshr i64 %x, 10
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%t11 = lshr i64 %x, 11
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%t12 = lshr i64 %x, 12
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%t13 = lshr i64 %x, 13
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%t14 = lshr i64 %x, 14
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%t15 = lshr i64 %x, 15
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%t16 = lshr i64 %x, 16
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%t17 = lshr i64 %x, 17
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%t18 = lshr i64 %x, 18
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%t19 = lshr i64 %x, 19
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%t20 = lshr i64 %x, 20
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%t21 = lshr i64 %x, 21
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%t22 = lshr i64 %x, 22
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%t23 = lshr i64 %x, 23
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%t24 = lshr i64 %x, 24
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%t25 = lshr i64 %x, 25
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%t26 = lshr i64 %x, 26
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%t27 = lshr i64 %x, 27
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%t28 = lshr i64 %x, 28
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%t29 = lshr i64 %x, 29
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%t30 = lshr i64 %x, 30
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%t31 = lshr i64 %x, 31
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%t32 = lshr i64 %x, 32
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%t33 = lshr i64 %x, 33
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%t34 = lshr i64 %x, 34
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%t35 = lshr i64 %x, 35
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%t36 = lshr i64 %x, 36
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%t37 = lshr i64 %x, 37
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%t38 = lshr i64 %x, 38
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%t39 = lshr i64 %x, 39
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%t40 = lshr i64 %x, 40
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%a1 = and i64 %t1, 1
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%a2 = and i64 %t2, %a1
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%a3 = and i64 %t3, %a2
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%a4 = and i64 %t4, %a3
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%a5 = and i64 %t5, %a4
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%a6 = and i64 %t6, %a5
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%a7 = and i64 %t7, %a6
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%a8 = and i64 %t8, %a7
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%a9 = and i64 %t9, %a8
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%a10 = and i64 %t10, %a9
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%a11 = and i64 %t11, %a10
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%a12 = and i64 %t12, %a11
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%a13 = and i64 %t13, %a12
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%a14 = and i64 %t14, %a13
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%a15 = and i64 %t15, %a14
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%a16 = and i64 %t16, %a15
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%a17 = and i64 %t17, %a16
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%a18 = and i64 %t18, %a17
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%a19 = and i64 %t19, %a18
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%a20 = and i64 %t20, %a19
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%a21 = and i64 %t21, %a20
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%a22 = and i64 %t22, %a21
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%a23 = and i64 %t23, %a22
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%a24 = and i64 %t24, %a23
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%a25 = and i64 %t25, %a24
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%a26 = and i64 %t26, %a25
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%a27 = and i64 %t27, %a26
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%a28 = and i64 %t28, %a27
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%a29 = and i64 %t29, %a28
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%a30 = and i64 %t30, %a29
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%a31 = and i64 %t31, %a30
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%a32 = and i64 %t32, %a31
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%a33 = and i64 %t33, %a32
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%a34 = and i64 %t34, %a33
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%a35 = and i64 %t35, %a34
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%a36 = and i64 %t36, %a35
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%a37 = and i64 %t37, %a36
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%a38 = and i64 %t38, %a37
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%a39 = and i64 %t39, %a38
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%a40 = and i64 %t40, %a39
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ret i64 %a40
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}
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; Verify that unsimplified code doesn't crash:
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; https://bugs.llvm.org/show_bug.cgi?id=37446
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define i32 @PR37446(i32 %x) {
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; CHECK-LABEL: @PR37446(
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; CHECK-NEXT: [[SHR:%.*]] = lshr i32 1, 33
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], 15
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; CHECK-NEXT: [[AND1:%.*]] = and i32 [[AND]], [[X:%.*]]
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; CHECK-NEXT: ret i32 [[AND1]]
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;
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%shr = lshr i32 1, 33
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%and = and i32 %shr, 15
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%and1 = and i32 %and, %x
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ret i32 %and1
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}
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