forked from OSchip/llvm-project
310 lines
10 KiB
C++
310 lines
10 KiB
C++
//===-- InstructionSnippetGeneratorTest.cpp ---------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "InstructionSnippetGenerator.h"
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#include "X86InstrInfo.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/Support/Host.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "gmock/gmock.h"
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#include "gtest/gtest.h"
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#include <memory>
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#include <set>
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namespace llvm {
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bool operator==(const MCOperand &A, const MCOperand &B) {
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if ((A.isValid() == false) && (B.isValid() == false))
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return true;
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if (A.isReg() && B.isReg())
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return A.getReg() == B.getReg();
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if (A.isImm() && B.isImm())
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return A.getImm() == B.getImm();
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return false;
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}
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} // namespace llvm
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namespace exegesis {
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namespace {
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using testing::_;
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using testing::AllOf;
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using testing::AnyOf;
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using testing::Contains;
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using testing::ElementsAre;
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using testing::Eq;
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using testing::Field;
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using testing::Not;
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using testing::SizeIs;
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using testing::UnorderedElementsAre;
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using testing::Value;
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using llvm::X86::AL;
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using llvm::X86::AX;
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using llvm::X86::EFLAGS;
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using llvm::X86::RAX;
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class MCInstrDescViewTest : public ::testing::Test {
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protected:
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MCInstrDescViewTest()
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: TheTriple("x86_64") {}
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static void SetUpTestCase() {
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LLVMInitializeX86TargetInfo();
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LLVMInitializeX86TargetMC();
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LLVMInitializeX86Target();
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}
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void SetUp() override {
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std::string Error;
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const auto *Target = llvm::TargetRegistry::lookupTarget(TheTriple, Error);
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InstrInfo.reset(Target->createMCInstrInfo());
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RegInfo.reset(Target->createMCRegInfo(TheTriple));
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}
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const std::string TheTriple;
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std::unique_ptr<const llvm::MCInstrInfo> InstrInfo;
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std::unique_ptr<const llvm::MCRegisterInfo> RegInfo;
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};
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MATCHER(IsDef, "") { return arg.IsDef; }
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MATCHER(IsUse, "") { return arg.IsUse; }
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MATCHER_P2(EqVarAssignement, VariableIndexMatcher, AssignedRegisterMatcher,
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"") {
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return Value(
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arg,
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AllOf(Field(&VariableAssignment::VarIdx, VariableIndexMatcher),
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Field(&VariableAssignment::AssignedReg, AssignedRegisterMatcher)));
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}
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size_t returnIndexZero(const size_t UpperBound) { return 0; }
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TEST_F(MCInstrDescViewTest, DISABLED_XOR64rr) {
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const llvm::MCInstrDesc &InstrDesc = InstrInfo->get(llvm::X86::XOR64rr);
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const auto Vars =
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getVariables(*RegInfo, InstrDesc, llvm::BitVector(RegInfo->getNumRegs()));
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// XOR64rr has the following operands:
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// 0. out register
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// 1. in register (tied to out)
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// 2. in register
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// 3. out EFLAGS (implicit)
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//
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// This translates to 3 variables, one for 0 and 1, one for 2, one for 3.
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ASSERT_THAT(Vars, SizeIs(3));
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EXPECT_THAT(Vars[0].ExplicitOperands, ElementsAre(0, 1));
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EXPECT_THAT(Vars[1].ExplicitOperands, ElementsAre(2));
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EXPECT_THAT(Vars[2].ExplicitOperands, ElementsAre()); // implicit
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EXPECT_THAT(Vars[0], AllOf(IsUse(), IsDef()));
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EXPECT_THAT(Vars[1], AllOf(IsUse(), Not(IsDef())));
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EXPECT_THAT(Vars[2], AllOf(Not(IsUse()), IsDef()));
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EXPECT_THAT(Vars[0].PossibleRegisters, Contains(RAX));
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EXPECT_THAT(Vars[1].PossibleRegisters, Contains(RAX));
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EXPECT_THAT(Vars[2].PossibleRegisters, ElementsAre(EFLAGS));
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// Computing chains.
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const auto Chains = computeSequentialAssignmentChains(*RegInfo, Vars);
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// Because operands 0 and 1 are tied together any possible value for variable
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// 0 would do.
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for (const auto &Reg : Vars[0].PossibleRegisters) {
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EXPECT_THAT(Chains, Contains(ElementsAre(EqVarAssignement(0, Reg))));
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}
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// We also have chains going through operand 0 to 2 (i.e. Vars 0 and 1).
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EXPECT_THAT(Vars[0].PossibleRegisters, Eq(Vars[1].PossibleRegisters))
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<< "Variables 0 and 1 are of the same class";
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for (const auto &Reg : Vars[0].PossibleRegisters) {
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EXPECT_THAT(Chains,
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Contains(UnorderedElementsAre(EqVarAssignement(0, Reg),
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EqVarAssignement(1, Reg))));
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}
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// EFLAGS does not appear as an input therefore no chain can contain EFLAGS.
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EXPECT_THAT(Chains, Not(Contains(Contains(EqVarAssignement(_, EFLAGS)))));
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// Computing assignment.
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const auto Regs = getRandomAssignment(Vars, Chains, &returnIndexZero);
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EXPECT_THAT(Regs, ElementsAre(RAX, RAX, EFLAGS));
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// Generating assembler representation.
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const llvm::MCInst Inst = generateMCInst(InstrDesc, Vars, Regs);
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EXPECT_THAT(Inst.getOpcode(), llvm::X86::XOR64rr);
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EXPECT_THAT(Inst.getNumOperands(), 3);
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EXPECT_THAT(Inst.getOperand(0), llvm::MCOperand::createReg(RAX));
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EXPECT_THAT(Inst.getOperand(1), llvm::MCOperand::createReg(RAX));
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EXPECT_THAT(Inst.getOperand(2), llvm::MCOperand::createReg(RAX));
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}
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TEST_F(MCInstrDescViewTest, DISABLED_AAA) {
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const llvm::MCInstrDesc &InstrDesc = InstrInfo->get(llvm::X86::AAA);
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const auto Vars =
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getVariables(*RegInfo, InstrDesc, llvm::BitVector(RegInfo->getNumRegs()));
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// AAA has the following operands:
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// 0. out AX (implicit)
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// 1. out EFLAGS (implicit)
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// 2. in AL (implicit)
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// 3. in EFLAGS (implicit)
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//
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// This translates to 4 Vars (non are tied together).
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ASSERT_THAT(Vars, SizeIs(4));
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EXPECT_THAT(Vars[0].ExplicitOperands, ElementsAre()); // implicit
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EXPECT_THAT(Vars[1].ExplicitOperands, ElementsAre()); // implicit
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EXPECT_THAT(Vars[2].ExplicitOperands, ElementsAre()); // implicit
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EXPECT_THAT(Vars[3].ExplicitOperands, ElementsAre()); // implicit
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EXPECT_THAT(Vars[0], AllOf(Not(IsUse()), IsDef()));
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EXPECT_THAT(Vars[1], AllOf(Not(IsUse()), IsDef()));
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EXPECT_THAT(Vars[2], AllOf(IsUse(), Not(IsDef())));
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EXPECT_THAT(Vars[3], AllOf(IsUse(), Not(IsDef())));
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EXPECT_THAT(Vars[0].PossibleRegisters, ElementsAre(AX));
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EXPECT_THAT(Vars[1].PossibleRegisters, ElementsAre(EFLAGS));
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EXPECT_THAT(Vars[2].PossibleRegisters, ElementsAre(AL));
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EXPECT_THAT(Vars[3].PossibleRegisters, ElementsAre(EFLAGS));
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const auto Chains = computeSequentialAssignmentChains(*RegInfo, Vars);
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EXPECT_THAT(Chains,
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ElementsAre(UnorderedElementsAre(EqVarAssignement(0, AX),
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EqVarAssignement(2, AL)),
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UnorderedElementsAre(EqVarAssignement(1, EFLAGS),
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EqVarAssignement(3, EFLAGS))));
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// Computing assignment.
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const auto Regs = getRandomAssignment(Vars, Chains, &returnIndexZero);
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EXPECT_THAT(Regs, ElementsAre(AX, EFLAGS, AL, EFLAGS));
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// Generating assembler representation.
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const llvm::MCInst Inst = generateMCInst(InstrDesc, Vars, Regs);
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EXPECT_THAT(Inst.getOpcode(), llvm::X86::AAA);
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EXPECT_THAT(Inst.getNumOperands(), 0) << "All operands are implicit";
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}
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TEST_F(MCInstrDescViewTest, DISABLED_ReservedRegisters) {
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llvm::BitVector ReservedRegisters(RegInfo->getNumRegs());
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const llvm::MCInstrDesc &InstrDesc = InstrInfo->get(llvm::X86::XOR64rr);
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{
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const auto Vars = getVariables(*RegInfo, InstrDesc, ReservedRegisters);
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ASSERT_THAT(Vars, SizeIs(3));
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EXPECT_THAT(Vars[0].PossibleRegisters, Contains(RAX));
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EXPECT_THAT(Vars[1].PossibleRegisters, Contains(RAX));
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}
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// Disable RAX.
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ReservedRegisters.set(RAX);
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{
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const auto Vars = getVariables(*RegInfo, InstrDesc, ReservedRegisters);
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ASSERT_THAT(Vars, SizeIs(3));
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EXPECT_THAT(Vars[0].PossibleRegisters, Not(Contains(RAX)));
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EXPECT_THAT(Vars[1].PossibleRegisters, Not(Contains(RAX)));
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}
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}
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Variable makeVariableWithRegisters(bool IsReg,
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std::initializer_list<int> Regs) {
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assert((IsReg || (Regs.size() == 0)) && "IsReg => !(Regs.size() == 0)");
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Variable Var;
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Var.IsReg = IsReg;
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Var.PossibleRegisters.insert(Regs.begin(), Regs.end());
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return Var;
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}
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TEST(getExclusiveAssignment, TriviallyFeasible) {
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const std::vector<Variable> Vars = {
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makeVariableWithRegisters(true, {3}),
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makeVariableWithRegisters(false, {}),
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makeVariableWithRegisters(true, {4}),
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makeVariableWithRegisters(true, {5}),
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};
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const auto Regs = getExclusiveAssignment(Vars);
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EXPECT_THAT(Regs, ElementsAre(3, 0, 4, 5));
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}
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TEST(getExclusiveAssignment, TriviallyInfeasible1) {
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const std::vector<Variable> Vars = {
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makeVariableWithRegisters(true, {3}),
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makeVariableWithRegisters(true, {}),
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makeVariableWithRegisters(true, {4}),
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makeVariableWithRegisters(true, {5}),
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};
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const auto Regs = getExclusiveAssignment(Vars);
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EXPECT_THAT(Regs, ElementsAre());
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}
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TEST(getExclusiveAssignment, TriviallyInfeasible) {
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const std::vector<Variable> Vars = {
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makeVariableWithRegisters(true, {4}),
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makeVariableWithRegisters(true, {4}),
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};
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const auto Regs = getExclusiveAssignment(Vars);
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EXPECT_THAT(Regs, ElementsAre());
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}
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TEST(getExclusiveAssignment, Feasible1) {
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const std::vector<Variable> Vars = {
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makeVariableWithRegisters(true, {4, 3}),
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makeVariableWithRegisters(true, {6, 3}),
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makeVariableWithRegisters(true, {6, 4}),
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};
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const auto Regs = getExclusiveAssignment(Vars);
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ASSERT_THAT(Regs, AnyOf(ElementsAre(3, 6, 4), ElementsAre(4, 3, 6)));
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}
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TEST(getExclusiveAssignment, Feasible2) {
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const std::vector<Variable> Vars = {
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makeVariableWithRegisters(true, {1, 2}),
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makeVariableWithRegisters(true, {3, 4}),
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};
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const auto Regs = getExclusiveAssignment(Vars);
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ASSERT_THAT(Regs, AnyOf(ElementsAre(1, 3), ElementsAre(1, 4),
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ElementsAre(2, 3), ElementsAre(2, 4)));
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}
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TEST(getGreedyAssignment, Infeasible) {
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const std::vector<Variable> Vars = {
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makeVariableWithRegisters(true, {}),
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makeVariableWithRegisters(true, {1, 2}),
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};
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const auto Regs = getGreedyAssignment(Vars);
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ASSERT_THAT(Regs, ElementsAre());
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}
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TEST(getGreedyAssignment, FeasibleNoFallback) {
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const std::vector<Variable> Vars = {
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makeVariableWithRegisters(true, {1, 2}),
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makeVariableWithRegisters(false, {}),
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makeVariableWithRegisters(true, {2, 3}),
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};
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const auto Regs = getGreedyAssignment(Vars);
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ASSERT_THAT(Regs, ElementsAre(1, 0, 2));
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}
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TEST(getGreedyAssignment, Feasible) {
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const std::vector<Variable> Vars = {
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makeVariableWithRegisters(false, {}),
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makeVariableWithRegisters(true, {1, 2}),
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makeVariableWithRegisters(true, {2, 3}),
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makeVariableWithRegisters(true, {2, 3}),
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makeVariableWithRegisters(true, {2, 3}),
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};
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const auto Regs = getGreedyAssignment(Vars);
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ASSERT_THAT(Regs, ElementsAre(0, 1, 2, 3, 2));
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}
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} // namespace
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} // namespace exegesis
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