forked from OSchip/llvm-project
233 lines
5.9 KiB
LLVM
233 lines
5.9 KiB
LLVM
; RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 %s -arm-disable-cgp=false -o - | FileCheck %s
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; CHECK: overflow_add
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; CHECK: add
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; CHECK: uxth
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; CHECK: cmp
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define zeroext i16 @overflow_add(i16 zeroext %a, i16 zeroext %b) {
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%add = add i16 %a, %b
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%or = or i16 %add, 1
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%cmp = icmp ugt i16 %or, 1024
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%res = select i1 %cmp, i16 2, i16 5
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ret i16 %res
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}
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; CHECK-LABEL: overflow_sub
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; CHECK: sub
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; CHECK: uxth
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; CHECK: cmp
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define zeroext i16 @overflow_sub(i16 zeroext %a, i16 zeroext %b) {
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%add = sub i16 %a, %b
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%or = or i16 %add, 1
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%cmp = icmp ugt i16 %or, 1024
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%res = select i1 %cmp, i16 2, i16 5
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ret i16 %res
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}
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; CHECK-LABEL: overflow_mul
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; CHECK: mul
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; CHECK: uxth
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; CHECK: cmp
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define zeroext i16 @overflow_mul(i16 zeroext %a, i16 zeroext %b) {
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%add = mul i16 %a, %b
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%or = or i16 %add, 1
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%cmp = icmp ugt i16 %or, 1024
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%res = select i1 %cmp, i16 2, i16 5
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ret i16 %res
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}
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; CHECK-LABEL: overflow_shl
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; CHECK-COMMON: lsl
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; CHECK-COMMON: uxth
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; CHECK-COMMON: cmp
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define zeroext i16 @overflow_shl(i16 zeroext %a, i16 zeroext %b) {
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%add = shl i16 %a, %b
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%or = or i16 %add, 1
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%cmp = icmp ugt i16 %or, 1024
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%res = select i1 %cmp, i16 2, i16 5
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ret i16 %res
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}
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; CHECK-LABEL: overflow_add_no_consts:
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; CHECK: add r0, r1
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; CHECK: uxtb [[EXT:r[0-9]+]], r0
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; CHECK: cmp [[EXT]], r2
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; CHECK: movhi r0, #8
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define i32 @overflow_add_no_consts(i8 zeroext %a, i8 zeroext %b, i8 zeroext %limit) {
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%add = add i8 %a, %b
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%cmp = icmp ugt i8 %add, %limit
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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; CHECK-LABEL: overflow_add_const_limit:
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; CHECK: add r0, r1
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; CHECK: uxtb [[EXT:r[0-9]+]], r0
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; CHECK: cmp [[EXT]], #128
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; CHECK: movhi r0, #8
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define i32 @overflow_add_const_limit(i8 zeroext %a, i8 zeroext %b) {
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%add = add i8 %a, %b
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%cmp = icmp ugt i8 %add, 128
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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; CHECK-LABEL: overflow_add_positive_const_limit:
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; CHECK: adds r0, #1
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; CHECK: uxtb [[EXT:r[0-9]+]], r0
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; CHECK: cmp [[EXT]], #128
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; CHECK: movhi r0, #8
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define i32 @overflow_add_positive_const_limit(i8 zeroext %a) {
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%add = add i8 %a, 1
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%cmp = icmp ugt i8 %add, 128
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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; CHECK-LABEL: unsafe_add_underflow:
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; CHECK: subs r0, #2
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; CHECK: uxtb [[EXT:r[0-9]+]], r0
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; CHECK: cmp [[EXT]], #255
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; CHECK: moveq r0, #8
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define i32 @unsafe_add_underflow(i8 zeroext %a) {
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%add = add i8 %a, -2
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%cmp = icmp ugt i8 %add, 254
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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; CHECK-LABEL: safe_add_underflow:
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; CHECK: subs [[MINUS_1:r[0-9]+]], r0, #1
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; CHECK-NOT: uxtb
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; CHECK: cmp [[MINUS_1]], #254
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; CHECK: movhi r0, #8
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define i32 @safe_add_underflow(i8 zeroext %a) {
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%add = add i8 %a, -1
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%cmp = icmp ugt i8 %add, 254
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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; CHECK-LABEL: safe_add_underflow_neg:
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; CHECK: subs [[MINUS_1:r[0-9]+]], r0, #2
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; CHECK-NOT: uxtb
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; CHECK: cmp [[MINUS_1]], #251
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; CHECK: movlo r0, #8
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define i32 @safe_add_underflow_neg(i8 zeroext %a) {
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%add = add i8 %a, -2
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%cmp = icmp ule i8 %add, -6
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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; CHECK-LABEL: overflow_sub_negative_const_limit:
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; CHECK: adds r0, #1
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; CHECK: uxtb [[EXT:r[0-9]+]], r0
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; CHECK: cmp [[EXT]], #128
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; CHECK: movhi r0, #8
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define i32 @overflow_sub_negative_const_limit(i8 zeroext %a) {
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%sub = sub i8 %a, -1
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%cmp = icmp ugt i8 %sub, 128
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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; CHECK-LABEL: unsafe_sub_underflow:
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; CHECK: subs r0, #6
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; CHECK: uxtb [[EXT:r[0-9]+]], r0
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; CHECK: cmp [[EXT]], #250
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; CHECK: movhi r0, #8
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define i32 @unsafe_sub_underflow(i8 zeroext %a) {
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%sub = sub i8 %a, 6
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%cmp = icmp ugt i8 %sub, 250
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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; CHECK-LABEL: safe_sub_underflow:
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; CHECK: subs [[MINUS_1:r[0-9]+]], r0, #1
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; CHECK-NOT: uxtb
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; CHECK: cmp [[MINUS_1]], #255
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; CHECK: movlo r0, #8
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define i32 @safe_sub_underflow(i8 zeroext %a) {
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%sub = sub i8 %a, 1
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%cmp = icmp ule i8 %sub, 254
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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; CHECK-LABEL: safe_sub_underflow_neg
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; CHECK: subs [[MINUS_1:r[0-9]+]], r0, #4
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; CHECK-NOT: uxtb
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; CHECK: cmp [[MINUS_1]], #250
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; CHECK: movhi r0, #8
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define i32 @safe_sub_underflow_neg(i8 zeroext %a) {
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%sub = sub i8 %a, 4
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%cmp = icmp uge i8 %sub, -5
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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; CHECK-LABEL: unsafe_sub_underflow_neg
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; CHECK: subs r0, #4
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; CHECK: uxtb [[EXT:r[0-9]+]], r0
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; CHECK: cmp [[EXT]], #253
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; CHECK: movlo r0, #8
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define i32 @unsafe_sub_underflow_neg(i8 zeroext %a) {
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%sub = sub i8 %a, 4
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%cmp = icmp ult i8 %sub, -3
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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; CHECK: rsb.w [[RSUB:r[0-9]+]], r0, #248
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; CHECK-NOT: uxt
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; CHECK: cmp [[RSUB]], #252
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define i32 @safe_sub_imm_var(i8* %b) {
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entry:
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%0 = load i8, i8* %b, align 1
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%sub = sub nuw nsw i8 -8, %0
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%cmp = icmp ugt i8 %sub, 252
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%conv4 = zext i1 %cmp to i32
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ret i32 %conv4
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}
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; CHECK-LABEL: safe_sub_var_imm
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; CHECK: add.w [[ADD:r[0-9]+]], r0, #8
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; CHECK-NOT: uxt
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; CHECK: cmp [[ADD]], #252
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define i32 @safe_sub_var_imm(i8* %b) {
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entry:
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%0 = load i8, i8* %b, align 1
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%sub = sub nuw nsw i8 %0, -8
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%cmp = icmp ugt i8 %sub, 252
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%conv4 = zext i1 %cmp to i32
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ret i32 %conv4
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}
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; CHECK-LABEL: safe_add_imm_var
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; CHECK: add.w [[ADD:r[0-9]+]], r0, #129
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; CHECK-NOT: uxt
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; CHECK: cmp [[ADD]], #127
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define i32 @safe_add_imm_var(i8* %b) {
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entry:
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%0 = load i8, i8* %b, align 1
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%add = add nuw nsw i8 -127, %0
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%cmp = icmp ugt i8 %add, 127
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%conv4 = zext i1 %cmp to i32
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ret i32 %conv4
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}
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; CHECK-LABEL: safe_add_var_imm
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; CHECK: sub.w [[SUB:r[0-9]+]], r0, #127
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; CHECK-NOT: uxt
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; CHECK: cmp [[SUB]], #127
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define i32 @safe_add_var_imm(i8* %b) {
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entry:
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%0 = load i8, i8* %b, align 1
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%add = add nuw nsw i8 %0, -127
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%cmp = icmp ugt i8 %add, 127
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%conv4 = zext i1 %cmp to i32
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ret i32 %conv4
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}
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