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AArch64
[GlobalISel] Fix equality for copies from physregs in matchEqualDefs
2020-03-27 17:52:21 -07:00
AMDGPU
[AMDGPU] Fix getEUsPerCU for gfx10 in CU mode
2020-03-27 20:36:49 +00:00
ARC
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ARM
[ARM] Move ConstantIsland and LowOverheadLoops Passes.
2020-03-25 16:49:21 +01:00
AVR
[AVR] Fix incorrect register state for LDRdPtr
2020-03-03 17:34:54 +08:00
BPF
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
Generic
[X86] Move combineLoopMAddPattern and combineLoopSADPattern to an IR pass before SelecitonDAG.
2020-03-26 14:10:20 -07:00
Hexagon
Revert "Include static prof data when collecting loop BBs"
2020-03-24 09:41:16 -07:00
Inputs
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Lanai
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
MIR
[AMDGPU] Move frame pointer from s34 to s33
2020-03-19 15:35:16 -04:00
MSP430
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Mips
[GlobalISel] combine G_TRUNC with G_MERGE_VALUES
2020-03-16 14:42:01 +01:00
NVPTX
CodeGen: Add -denormal-fp-math-f32 flag
2020-03-27 14:00:39 -07:00
PowerPC
[FEnv] Constfold some unary constrained operations
2020-03-28 12:28:33 +07:00
RISCV
[RISCV] Support llvm.thread.pointer
2020-03-27 17:30:12 -07:00
SPARC
[Sparc] Fix incorrect operand for matching CMPri pattern
2020-03-02 11:36:32 +08:00
SystemZ
[SystemZ] Improve foldMemoryOperandImpl()
2020-03-25 16:21:08 +01:00
Thumb
[DAGCombine] Skip PostInc combine with later users
2020-03-23 08:39:53 +00:00
Thumb2
[ARM][LowOverheadLoops] DoubleWidthResult instructions canGenerateZeros
2020-03-27 15:26:13 +00:00
VE
[VE] Target-specific bit size for sjljehprepare
2020-03-10 17:51:16 +01:00
WebAssembly
[WebAssembly] Fix the order of destructors in the LowerGlobalDtors pass.
2020-03-26 16:19:02 -07:00
WinCFGuard
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WinEH
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X86
[X86] Don't form masked instructions if the operation has an additional user.
2020-03-27 10:44:22 -07:00
XCore
[XCore] Add instruction pattern for bitrev
2020-02-21 09:28:49 +08:00
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