Matt Arsenault 362f345bab R600/SI: Fix off by 1 error in used register count ... The register numbers start at 0, so if only 1 register was used, this was reported as 0. llvm-svn: 217636		2014-09-11 22:51:37 +00:00
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AArch64	Add DAG combine for shl + add of constants.	2014-09-11 17:34:19 +00:00
ARM	[ARM] Add Thumb-2 code size optimization regression test for LSR (register).	2014-09-11 10:45:50 +00:00
CPP	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Generic	Add a regression test to sanity check the PBQP allocator.	2014-09-03 18:04:10 +00:00
Hexagon	DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.	2014-08-06 00:21:25 +00:00
Inputs	…
MSP430	Drop the W postfix on the 16-bit registers.	2014-09-10 06:58:14 +00:00
Mips	Replace -use-init-array with -use-ctors.	2014-09-02 13:54:53 +00:00
NVPTX	[MachineSink] Use the real post dominator tree	2014-09-01 03:47:25 +00:00
PowerPC	Add missing colon to RUN line...	2014-09-11 20:13:52 +00:00
R600	R600/SI: Fix off by 1 error in used register count	2014-09-11 22:51:37 +00:00
SPARC	Provide an implementation of getNoopForMachoTarget for SPARC.	2014-09-11 17:40:51 +00:00
SystemZ	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Thumb	Check-label a bit more specific	2014-09-03 13:32:08 +00:00
Thumb2	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
X86	[CodeGenPrepare] Teach the addressing mode matcher how to promote zext.	2014-09-11 21:22:14 +00:00
XCore	llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.	2014-07-04 11:58:03 +00:00