forked from OSchip/llvm-project
508 lines
17 KiB
C++
508 lines
17 KiB
C++
//===-- X86AsmInstrumentation.cpp - Instrument X86 inline assembly C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "X86AsmInstrumentation.h"
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#include "X86Operand.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCTargetAsmParser.h"
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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namespace llvm {
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namespace {
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static cl::opt<bool> ClAsanInstrumentAssembly(
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"asan-instrument-assembly",
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cl::desc("instrument assembly with AddressSanitizer checks"), cl::Hidden,
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cl::init(false));
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bool IsStackReg(unsigned Reg) {
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return Reg == X86::RSP || Reg == X86::ESP || Reg == X86::SP;
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}
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std::string FuncName(unsigned AccessSize, bool IsWrite) {
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return std::string("__asan_report_") + (IsWrite ? "store" : "load") +
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utostr(AccessSize);
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}
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class X86AddressSanitizer : public X86AsmInstrumentation {
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public:
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X86AddressSanitizer(const MCSubtargetInfo &STI) : STI(STI) {}
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virtual ~X86AddressSanitizer() {}
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// X86AsmInstrumentation implementation:
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virtual void InstrumentInstruction(
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const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
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const MCInstrInfo &MII, MCStreamer &Out) override {
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InstrumentMOV(Inst, Operands, Ctx, MII, Out);
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}
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// Should be implemented differently in x86_32 and x86_64 subclasses.
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virtual void InstrumentMemOperandSmallImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) = 0;
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virtual void InstrumentMemOperandLargeImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) = 0;
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void InstrumentMemOperand(MCParsedAsmOperand &Op, unsigned AccessSize,
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bool IsWrite, MCContext &Ctx, MCStreamer &Out);
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void InstrumentMOV(const MCInst &Inst, OperandVector &Operands,
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MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
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void EmitInstruction(MCStreamer &Out, const MCInst &Inst) {
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Out.EmitInstruction(Inst, STI);
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}
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void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); }
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protected:
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const MCSubtargetInfo &STI;
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};
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void X86AddressSanitizer::InstrumentMemOperand(
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MCParsedAsmOperand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) {
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assert(Op.isMem() && "Op should be a memory operand.");
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assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 &&
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"AccessSize should be a power of two, less or equal than 16.");
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X86Operand &MemOp = static_cast<X86Operand &>(Op);
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// FIXME: get rid of this limitation.
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if (IsStackReg(MemOp.getMemBaseReg()) || IsStackReg(MemOp.getMemIndexReg()))
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return;
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// FIXME: take into account load/store alignment.
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if (AccessSize < 8)
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InstrumentMemOperandSmallImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
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else
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InstrumentMemOperandLargeImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
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}
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void X86AddressSanitizer::InstrumentMOV(
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const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
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const MCInstrInfo &MII, MCStreamer &Out) {
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// Access size in bytes.
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unsigned AccessSize = 0;
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switch (Inst.getOpcode()) {
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case X86::MOV8mi:
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case X86::MOV8mr:
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case X86::MOV8rm:
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AccessSize = 1;
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break;
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case X86::MOV16mi:
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case X86::MOV16mr:
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case X86::MOV16rm:
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AccessSize = 2;
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break;
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case X86::MOV32mi:
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case X86::MOV32mr:
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case X86::MOV32rm:
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AccessSize = 4;
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break;
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case X86::MOV64mi32:
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case X86::MOV64mr:
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case X86::MOV64rm:
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AccessSize = 8;
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break;
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case X86::MOVAPDmr:
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case X86::MOVAPSmr:
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case X86::MOVAPDrm:
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case X86::MOVAPSrm:
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AccessSize = 16;
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break;
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default:
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return;
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}
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const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
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for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
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assert(Operands[Ix]);
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MCParsedAsmOperand &Op = *Operands[Ix];
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if (Op.isMem())
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InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
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}
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}
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class X86AddressSanitizer32 : public X86AddressSanitizer {
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public:
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static const long kShadowOffset = 0x20000000;
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X86AddressSanitizer32(const MCSubtargetInfo &STI)
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: X86AddressSanitizer(STI) {}
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virtual ~X86AddressSanitizer32() {}
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virtual void InstrumentMemOperandSmallImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) override;
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virtual void InstrumentMemOperandLargeImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) override;
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private:
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void EmitCallAsanReport(MCContext &Ctx, MCStreamer &Out, unsigned AccessSize,
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bool IsWrite, unsigned AddressReg) {
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EmitInstruction(Out, MCInstBuilder(X86::CLD));
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EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
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EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::ESP)
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.addReg(X86::ESP).addImm(-16));
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(AddressReg));
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const std::string& Fn = FuncName(AccessSize, IsWrite);
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MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
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const MCSymbolRefExpr *FnExpr =
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MCSymbolRefExpr::Create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
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EmitInstruction(Out, MCInstBuilder(X86::CALLpcrel32).addExpr(FnExpr));
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}
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};
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void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) {
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EDX));
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EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
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{
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MCInst Inst;
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Inst.setOpcode(X86::LEA32r);
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Inst.addOperand(MCOperand::CreateReg(X86::EAX));
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Op.addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX)
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.addReg(X86::ECX).addImm(3));
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{
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MCInst Inst;
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Inst.setOpcode(X86::MOV8rm);
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Inst.addOperand(MCOperand::CreateReg(X86::CL));
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const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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EmitInstruction(Out,
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MCInstBuilder(X86::TEST8rr).addReg(X86::CL).addReg(X86::CL));
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MCSymbol *DoneSym = Ctx.CreateTempSymbol();
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const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
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EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV32rr).addReg(X86::EDX).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::AND32ri).addReg(X86::EDX)
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.addReg(X86::EDX).addImm(7));
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switch (AccessSize) {
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case 1:
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break;
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case 2: {
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MCInst Inst;
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Inst.setOpcode(X86::LEA32r);
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Inst.addOperand(MCOperand::CreateReg(X86::EDX));
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const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc()));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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break;
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}
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case 4:
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EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::EDX)
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.addReg(X86::EDX).addImm(3));
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break;
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default:
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assert(false && "Incorrect access size");
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break;
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}
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EmitInstruction(
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Out, MCInstBuilder(X86::MOVSX32rr8).addReg(X86::ECX).addReg(X86::CL));
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EmitInstruction(
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Out, MCInstBuilder(X86::CMP32rr).addReg(X86::EDX).addReg(X86::ECX));
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EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
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EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite, X86::EAX);
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EmitLabel(Out, DoneSym);
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EmitInstruction(Out, MCInstBuilder(X86::POPF32));
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EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EDX));
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EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::ECX));
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EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
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}
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void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) {
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
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EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
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{
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MCInst Inst;
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Inst.setOpcode(X86::LEA32r);
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Inst.addOperand(MCOperand::CreateReg(X86::EAX));
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Op.addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX)
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.addReg(X86::ECX).addImm(3));
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{
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MCInst Inst;
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switch (AccessSize) {
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case 8:
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Inst.setOpcode(X86::CMP8mi);
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break;
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case 16:
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Inst.setOpcode(X86::CMP16mi);
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break;
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default:
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assert(false && "Incorrect access size");
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break;
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}
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const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
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Op->addMemOperands(Inst, 5);
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Inst.addOperand(MCOperand::CreateImm(0));
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EmitInstruction(Out, Inst);
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}
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MCSymbol *DoneSym = Ctx.CreateTempSymbol();
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const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
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EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
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EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite, X86::EAX);
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EmitLabel(Out, DoneSym);
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EmitInstruction(Out, MCInstBuilder(X86::POPF32));
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EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::ECX));
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EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
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}
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class X86AddressSanitizer64 : public X86AddressSanitizer {
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public:
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static const long kShadowOffset = 0x7fff8000;
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X86AddressSanitizer64(const MCSubtargetInfo &STI)
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: X86AddressSanitizer(STI) {}
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virtual ~X86AddressSanitizer64() {}
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virtual void InstrumentMemOperandSmallImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) override;
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virtual void InstrumentMemOperandLargeImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) override;
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private:
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void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) {
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MCInst Inst;
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Inst.setOpcode(X86::LEA64r);
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Inst.addOperand(MCOperand::CreateReg(X86::RSP));
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const MCExpr *Disp = MCConstantExpr::Create(Offset, Ctx);
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc()));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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void EmitCallAsanReport(MCContext &Ctx, MCStreamer &Out, unsigned AccessSize,
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bool IsWrite) {
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EmitInstruction(Out, MCInstBuilder(X86::CLD));
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EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
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EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::RSP)
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.addReg(X86::RSP).addImm(-16));
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const std::string& Fn = FuncName(AccessSize, IsWrite);
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MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
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const MCSymbolRefExpr *FnExpr =
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MCSymbolRefExpr::Create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
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EmitInstruction(Out, MCInstBuilder(X86::CALL64pcrel32).addExpr(FnExpr));
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}
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};
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void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) {
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EmitAdjustRSP(Ctx, Out, -128);
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EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
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EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RCX));
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EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RDI));
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EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
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{
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MCInst Inst;
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Inst.setOpcode(X86::LEA64r);
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Inst.addOperand(MCOperand::CreateReg(X86::RDI));
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Op.addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RAX).addReg(X86::RDI));
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EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX)
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.addReg(X86::RAX).addImm(3));
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{
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MCInst Inst;
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Inst.setOpcode(X86::MOV8rm);
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Inst.addOperand(MCOperand::CreateReg(X86::AL));
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const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc()));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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EmitInstruction(Out,
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MCInstBuilder(X86::TEST8rr).addReg(X86::AL).addReg(X86::AL));
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MCSymbol *DoneSym = Ctx.CreateTempSymbol();
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const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
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EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EDI));
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EmitInstruction(Out, MCInstBuilder(X86::AND32ri).addReg(X86::ECX)
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.addReg(X86::ECX).addImm(7));
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switch (AccessSize) {
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case 1:
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break;
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case 2: {
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MCInst Inst;
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Inst.setOpcode(X86::LEA32r);
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Inst.addOperand(MCOperand::CreateReg(X86::ECX));
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const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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break;
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}
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case 4:
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EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::ECX)
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.addReg(X86::ECX).addImm(3));
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break;
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default:
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assert(false && "Incorrect access size");
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break;
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}
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EmitInstruction(
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Out, MCInstBuilder(X86::MOVSX32rr8).addReg(X86::EAX).addReg(X86::AL));
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EmitInstruction(
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Out, MCInstBuilder(X86::CMP32rr).addReg(X86::ECX).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
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EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite);
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EmitLabel(Out, DoneSym);
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EmitInstruction(Out, MCInstBuilder(X86::POPF64));
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EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RDI));
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EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RCX));
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EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RAX));
|
|
EmitAdjustRSP(Ctx, Out, 128);
|
|
}
|
|
|
|
void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(
|
|
X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
|
|
MCStreamer &Out) {
|
|
EmitAdjustRSP(Ctx, Out, -128);
|
|
EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
|
|
EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
|
|
|
|
{
|
|
MCInst Inst;
|
|
Inst.setOpcode(X86::LEA64r);
|
|
Inst.addOperand(MCOperand::CreateReg(X86::RAX));
|
|
Op.addMemOperands(Inst, 5);
|
|
EmitInstruction(Out, Inst);
|
|
}
|
|
EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX)
|
|
.addReg(X86::RAX).addImm(3));
|
|
{
|
|
MCInst Inst;
|
|
switch (AccessSize) {
|
|
case 8:
|
|
Inst.setOpcode(X86::CMP8mi);
|
|
break;
|
|
case 16:
|
|
Inst.setOpcode(X86::CMP16mi);
|
|
break;
|
|
default:
|
|
assert(false && "Incorrect access size");
|
|
break;
|
|
}
|
|
const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
|
|
std::unique_ptr<X86Operand> Op(
|
|
X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc()));
|
|
Op->addMemOperands(Inst, 5);
|
|
Inst.addOperand(MCOperand::CreateImm(0));
|
|
EmitInstruction(Out, Inst);
|
|
}
|
|
|
|
MCSymbol *DoneSym = Ctx.CreateTempSymbol();
|
|
const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
|
|
EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
|
|
|
|
EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite);
|
|
EmitLabel(Out, DoneSym);
|
|
|
|
EmitInstruction(Out, MCInstBuilder(X86::POPF64));
|
|
EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RAX));
|
|
EmitAdjustRSP(Ctx, Out, 128);
|
|
}
|
|
|
|
} // End anonymous namespace
|
|
|
|
X86AsmInstrumentation::X86AsmInstrumentation() {}
|
|
X86AsmInstrumentation::~X86AsmInstrumentation() {}
|
|
|
|
void X86AsmInstrumentation::InstrumentInstruction(
|
|
const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
|
|
const MCInstrInfo &MII, MCStreamer &Out) {}
|
|
|
|
X86AsmInstrumentation *
|
|
CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
|
|
const MCContext &Ctx, const MCSubtargetInfo &STI) {
|
|
Triple T(STI.getTargetTriple());
|
|
const bool hasCompilerRTSupport = T.isOSLinux();
|
|
if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
|
|
MCOptions.SanitizeAddress) {
|
|
if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
|
|
return new X86AddressSanitizer32(STI);
|
|
if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)
|
|
return new X86AddressSanitizer64(STI);
|
|
}
|
|
return new X86AsmInstrumentation();
|
|
}
|
|
|
|
} // End llvm namespace
|