forked from OSchip/llvm-project
525 lines
25 KiB
C++
525 lines
25 KiB
C++
//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Hexagon implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Support/MachineValueType.h"
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#include <cstdint>
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#include <vector>
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#define GET_INSTRINFO_HEADER
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#include "HexagonGenInstrInfo.inc"
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namespace llvm {
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class HexagonSubtarget;
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class MachineBranchProbabilityInfo;
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class MachineFunction;
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class MachineInstr;
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class MachineOperand;
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class TargetRegisterInfo;
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class HexagonInstrInfo : public HexagonGenInstrInfo {
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const HexagonSubtarget &Subtarget;
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enum BundleAttribute {
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memShufDisabledMask = 0x4
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};
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virtual void anchor();
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public:
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explicit HexagonInstrInfo(HexagonSubtarget &ST);
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/// TargetInstrInfo overrides.
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/// If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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/// If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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/// Check if the instruction or the bundle of instructions has
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/// load from stack slots. Return the frameindex and machine memory operand
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/// if true.
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bool hasLoadFromStackSlot(
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const MachineInstr &MI,
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SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
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/// Check if the instruction or the bundle of instructions has
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/// store to stack slots. Return the frameindex and machine memory operand
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/// if true.
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bool hasStoreToStackSlot(
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const MachineInstr &MI,
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SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
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/// Analyze the branching code at the end of MBB, returning
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/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
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/// implemented for a target). Upon success, this returns false and returns
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/// with the following information in various cases:
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///
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/// 1. If this block ends with no branches (it just falls through to its succ)
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/// just return false, leaving TBB/FBB null.
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/// 2. If this block ends with only an unconditional branch, it sets TBB to be
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/// the destination block.
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/// 3. If this block ends with a conditional branch and it falls through to a
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/// successor block, it sets TBB to be the branch destination block and a
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/// list of operands that evaluate the condition. These operands can be
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/// passed to other TargetInstrInfo methods to create new branches.
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/// 4. If this block ends with a conditional branch followed by an
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/// unconditional branch, it returns the 'true' destination in TBB, the
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/// 'false' destination in FBB, and a list of operands that evaluate the
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/// condition. These operands can be passed to other TargetInstrInfo
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/// methods to create new branches.
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///
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/// Note that removeBranch and insertBranch must be implemented to support
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/// cases where this method returns success.
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///
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/// If AllowModify is true, then this routine is allowed to modify the basic
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/// block (e.g. delete instructions after the unconditional branch).
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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/// Remove the branching code at the end of the specific MBB.
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/// This is only invoked in cases where AnalyzeBranch returns success. It
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/// returns the number of instructions that were removed.
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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/// Insert branch code into the end of the specified MachineBasicBlock.
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/// The operands to this method are the same as those
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/// returned by AnalyzeBranch. This is only invoked in cases where
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/// AnalyzeBranch returns success. It returns the number of instructions
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/// inserted.
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///
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/// It is also invoked by tail merging to add unconditional branches in
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/// cases where AnalyzeBranch doesn't apply because there was no original
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/// branch to analyze. At least this much must be implemented, else tail
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/// merging needs to be disabled.
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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/// Analyze the loop code, return true if it cannot be understood. Upon
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/// success, this function returns false and returns information about the
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/// induction variable and compare instruction used at the end.
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bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
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MachineInstr *&CmpInst) const override;
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/// Generate code to reduce the loop iteration by one and check if the loop
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/// is finished. Return the value/register of the new loop count. We need
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/// this function when peeling off one or more iterations of a loop. This
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/// function assumes the nth iteration is peeled first.
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unsigned reduceLoopCount(MachineBasicBlock &MBB,
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MachineInstr *IndVar, MachineInstr &Cmp,
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SmallVectorImpl<MachineOperand> &Cond,
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SmallVectorImpl<MachineInstr *> &PrevInsts,
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unsigned Iter, unsigned MaxIter) const override;
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/// Return true if it's profitable to predicate
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/// instructions with accumulated instruction latency of "NumCycles"
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/// of the specified basic block, where the probability of the instructions
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/// being executed is given by Probability, and Confidence is a measure
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/// of our confidence that it will be properly predicted.
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bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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unsigned ExtraPredCycles,
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BranchProbability Probability) const override;
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/// Second variant of isProfitableToIfCvt. This one
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/// checks for the case where two basic blocks from true and false path
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/// of a if-then-else (diamond) are predicated on mutally exclusive
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/// predicates, where the probability of the true path being taken is given
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/// by Probability, and Confidence is a measure of our confidence that it
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/// will be properly predicted.
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bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumTCycles, unsigned ExtraTCycles,
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MachineBasicBlock &FMBB,
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unsigned NumFCycles, unsigned ExtraFCycles,
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BranchProbability Probability) const override;
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/// Return true if it's profitable for if-converter to duplicate instructions
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/// of specified accumulated instruction latencies in the specified MBB to
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/// enable if-conversion.
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/// The probability of the instructions being executed is given by
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/// Probability, and Confidence is a measure of our confidence that it
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/// will be properly predicted.
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bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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BranchProbability Probability) const override;
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/// Emit instructions to copy a pair of physical registers.
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///
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/// This function should support copies within any legal register class as
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/// well as any cross-class copies created during instruction selection.
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///
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/// The source and destination registers may overlap, which may require a
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/// careful implementation when multiple copy instructions are required for
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/// large registers. See for example the ARM target.
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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/// Store the specified register of the given register class to the specified
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/// stack frame index. The store instruction is to be added to the given
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/// machine basic block before the specified machine instruction. If isKill
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/// is true, the register operand is the last use and must be marked kill.
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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/// Load the specified register of the given register class from the specified
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/// stack frame index. The load instruction is to be added to the given
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/// machine basic block before the specified machine instruction.
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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/// This function is called for all pseudo instructions
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/// that remain after register allocation. Many pseudo instructions are
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/// created to help register allocation. This is the place to convert them
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/// into real instructions. The target can edit MI in place, or it can insert
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/// new instructions and erase MI. The function should return true if
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/// anything was changed.
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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/// Get the base register and byte offset of a load/store instr.
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bool getMemOperandWithOffset(MachineInstr &LdSt, MachineOperand *&BaseOp,
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int64_t &Offset,
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const TargetRegisterInfo *TRI) const override;
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/// Reverses the branch condition of the specified condition list,
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/// returning false on success and true if it cannot be reversed.
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bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
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const override;
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/// Insert a noop into the instruction stream at the specified point.
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void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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/// Returns true if the instruction is already predicated.
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bool isPredicated(const MachineInstr &MI) const override;
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/// Return true for post-incremented instructions.
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bool isPostIncrement(const MachineInstr &MI) const override;
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/// Convert the instruction into a predicated instruction.
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/// It returns true if the operation was successful.
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bool PredicateInstruction(MachineInstr &MI,
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ArrayRef<MachineOperand> Cond) const override;
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/// Returns true if the first specified predicate
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/// subsumes the second, e.g. GE subsumes GT.
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bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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ArrayRef<MachineOperand> Pred2) const override;
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/// If the specified instruction defines any predicate
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/// or condition code register(s) used for predication, returns true as well
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/// as the definition predicate(s) by reference.
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bool DefinesPredicate(MachineInstr &MI,
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std::vector<MachineOperand> &Pred) const override;
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/// Return true if the specified instruction can be predicated.
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/// By default, this returns true for every instruction with a
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/// PredicateOperand.
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bool isPredicable(const MachineInstr &MI) const override;
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/// Test if the given instruction should be considered a scheduling boundary.
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/// This primarily includes labels and terminators.
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bool isSchedulingBoundary(const MachineInstr &MI,
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const MachineBasicBlock *MBB,
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const MachineFunction &MF) const override;
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/// Measure the specified inline asm to determine an approximation of its
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/// length.
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unsigned getInlineAsmLength(const char *Str,
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const MCAsmInfo &MAI) const override;
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/// Allocate and return a hazard recognizer to use for this target when
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/// scheduling the machine instructions after register allocation.
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ScheduleHazardRecognizer*
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CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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const ScheduleDAG *DAG) const override;
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/// For a comparison instruction, return the source registers
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/// in SrcReg and SrcReg2 if having two register operands, and the value it
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/// compares against in CmpValue. Return true if the comparison instruction
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/// can be analyzed.
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bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
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unsigned &SrcReg2, int &Mask, int &Value) const override;
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/// Compute the instruction latency of a given instruction.
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/// If the instruction has higher cost when predicated, it's returned via
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/// PredCost.
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unsigned getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr &MI,
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unsigned *PredCost = nullptr) const override;
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/// Create machine specific model for scheduling.
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DFAPacketizer *
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CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
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// Sometimes, it is possible for the target
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// to tell, even without aliasing information, that two MIs access different
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// memory addresses. This function returns true if two MIs access different
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// memory addresses and false otherwise.
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bool
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areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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AliasAnalysis *AA = nullptr) const override;
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/// For instructions with a base and offset, return the position of the
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/// base register and offset operands.
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bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
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unsigned &OffsetPos) const override;
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/// If the instruction is an increment of a constant value, return the amount.
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bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
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/// getOperandLatency - Compute and return the use operand latency of a given
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/// pair of def and use.
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/// In most cases, the static scheduling itinerary was enough to determine the
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/// operand latency. But it may not be possible for instructions with variable
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/// number of defs / uses.
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///
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/// This is a raw interface to the itinerary that may be directly overriden by
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/// a target. Use computeOperandLatency to get the best estimate of latency.
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int getOperandLatency(const InstrItineraryData *ItinData,
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const MachineInstr &DefMI, unsigned DefIdx,
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const MachineInstr &UseMI,
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unsigned UseIdx) const override;
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/// Decompose the machine operand's target flags into two values - the direct
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/// target flag value and any of bit flags that are applied.
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std::pair<unsigned, unsigned>
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decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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/// Return an array that contains the direct target flag values and their
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/// names.
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///
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/// MIR Serialization is able to serialize only the target flags that are
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/// defined by this method.
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableDirectMachineOperandTargetFlags() const override;
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/// Return an array that contains the bitmask target flag values and their
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/// names.
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///
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/// MIR Serialization is able to serialize only the target flags that are
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/// defined by this method.
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableBitmaskMachineOperandTargetFlags() const override;
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bool isTailCall(const MachineInstr &MI) const override;
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/// HexagonInstrInfo specifics.
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unsigned createVR(MachineFunction *MF, MVT VT) const;
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MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp,
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MachineBasicBlock *TargetBB,
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SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
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bool isBaseImmOffset(const MachineInstr &MI) const;
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bool isAbsoluteSet(const MachineInstr &MI) const;
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bool isAccumulator(const MachineInstr &MI) const;
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bool isAddrModeWithOffset(const MachineInstr &MI) const;
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bool isComplex(const MachineInstr &MI) const;
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bool isCompoundBranchInstr(const MachineInstr &MI) const;
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bool isConstExtended(const MachineInstr &MI) const;
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bool isDeallocRet(const MachineInstr &MI) const;
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bool isDependent(const MachineInstr &ProdMI,
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const MachineInstr &ConsMI) const;
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bool isDotCurInst(const MachineInstr &MI) const;
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bool isDotNewInst(const MachineInstr &MI) const;
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bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
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bool isEarlySourceInstr(const MachineInstr &MI) const;
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bool isEndLoopN(unsigned Opcode) const;
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bool isExpr(unsigned OpType) const;
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bool isExtendable(const MachineInstr &MI) const;
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bool isExtended(const MachineInstr &MI) const;
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bool isFloat(const MachineInstr &MI) const;
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bool isHVXMemWithAIndirect(const MachineInstr &I,
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const MachineInstr &J) const;
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bool isIndirectCall(const MachineInstr &MI) const;
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bool isIndirectL4Return(const MachineInstr &MI) const;
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bool isJumpR(const MachineInstr &MI) const;
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bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const;
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bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
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const MachineInstr &ESMI) const;
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bool isLateResultInstr(const MachineInstr &MI) const;
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bool isLateSourceInstr(const MachineInstr &MI) const;
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bool isLoopN(const MachineInstr &MI) const;
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bool isMemOp(const MachineInstr &MI) const;
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bool isNewValue(const MachineInstr &MI) const;
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bool isNewValue(unsigned Opcode) const;
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bool isNewValueInst(const MachineInstr &MI) const;
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bool isNewValueJump(const MachineInstr &MI) const;
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bool isNewValueJump(unsigned Opcode) const;
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bool isNewValueStore(const MachineInstr &MI) const;
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bool isNewValueStore(unsigned Opcode) const;
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bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const;
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bool isPredicatedNew(const MachineInstr &MI) const;
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bool isPredicatedNew(unsigned Opcode) const;
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bool isPredicatedTrue(const MachineInstr &MI) const;
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bool isPredicatedTrue(unsigned Opcode) const;
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bool isPredicated(unsigned Opcode) const;
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bool isPredicateLate(unsigned Opcode) const;
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bool isPredictedTaken(unsigned Opcode) const;
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bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const;
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bool isSignExtendingLoad(const MachineInstr &MI) const;
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bool isSolo(const MachineInstr &MI) const;
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bool isSpillPredRegOp(const MachineInstr &MI) const;
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bool isTC1(const MachineInstr &MI) const;
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bool isTC2(const MachineInstr &MI) const;
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bool isTC2Early(const MachineInstr &MI) const;
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bool isTC4x(const MachineInstr &MI) const;
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bool isToBeScheduledASAP(const MachineInstr &MI1,
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const MachineInstr &MI2) const;
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bool isHVXVec(const MachineInstr &MI) const;
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bool isValidAutoIncImm(const EVT VT, const int Offset) const;
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bool isValidOffset(unsigned Opcode, int Offset,
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const TargetRegisterInfo *TRI, bool Extend = true) const;
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bool isVecAcc(const MachineInstr &MI) const;
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bool isVecALU(const MachineInstr &MI) const;
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bool isVecUsableNextPacket(const MachineInstr &ProdMI,
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const MachineInstr &ConsMI) const;
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bool isZeroExtendingLoad(const MachineInstr &MI) const;
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bool addLatencyToSchedule(const MachineInstr &MI1,
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const MachineInstr &MI2) const;
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bool canExecuteInBundle(const MachineInstr &First,
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const MachineInstr &Second) const;
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bool doesNotReturn(const MachineInstr &CallMI) const;
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bool hasEHLabel(const MachineBasicBlock *B) const;
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bool hasNonExtEquivalent(const MachineInstr &MI) const;
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bool hasPseudoInstrPair(const MachineInstr &MI) const;
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bool hasUncondBranch(const MachineBasicBlock *B) const;
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bool mayBeCurLoad(const MachineInstr &MI) const;
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bool mayBeNewStore(const MachineInstr &MI) const;
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bool producesStall(const MachineInstr &ProdMI,
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const MachineInstr &ConsMI) const;
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bool producesStall(const MachineInstr &MI,
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MachineBasicBlock::const_instr_iterator MII) const;
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bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const;
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bool PredOpcodeHasJMP_c(unsigned Opcode) const;
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bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
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unsigned getAddrMode(const MachineInstr &MI) const;
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MachineOperand *getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
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unsigned &AccessSize) const;
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SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
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unsigned getCExtOpNum(const MachineInstr &MI) const;
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HexagonII::CompoundGroup
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getCompoundCandidateGroup(const MachineInstr &MI) const;
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unsigned getCompoundOpcode(const MachineInstr &GA,
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const MachineInstr &GB) const;
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int getCondOpcode(int Opc, bool sense) const;
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int getDotCurOp(const MachineInstr &MI) const;
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int getNonDotCurOp(const MachineInstr &MI) const;
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int getDotNewOp(const MachineInstr &MI) const;
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int getDotNewPredJumpOp(const MachineInstr &MI,
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const MachineBranchProbabilityInfo *MBPI) const;
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int getDotNewPredOp(const MachineInstr &MI,
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const MachineBranchProbabilityInfo *MBPI) const;
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int getDotOldOp(const MachineInstr &MI) const;
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HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI)
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const;
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short getEquivalentHWInstr(const MachineInstr &MI) const;
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unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
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const MachineInstr &MI) const;
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bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
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unsigned getInvertedPredicatedOpcode(const int Opc) const;
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int getMaxValue(const MachineInstr &MI) const;
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unsigned getMemAccessSize(const MachineInstr &MI) const;
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int getMinValue(const MachineInstr &MI) const;
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short getNonExtOpcode(const MachineInstr &MI) const;
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bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
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unsigned &PredRegPos, unsigned &PredRegFlags) const;
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short getPseudoInstrPair(const MachineInstr &MI) const;
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short getRegForm(const MachineInstr &MI) const;
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unsigned getSize(const MachineInstr &MI) const;
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uint64_t getType(const MachineInstr &MI) const;
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unsigned getUnits(const MachineInstr &MI) const;
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MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const;
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/// getInstrTimingClassLatency - Compute the instruction latency of a given
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/// instruction using Timing Class information, if available.
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unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
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unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
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void immediateExtend(MachineInstr &MI) const;
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bool invertAndChangeJumpTarget(MachineInstr &MI,
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MachineBasicBlock *NewTarget) const;
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void genAllInsnTimingClasses(MachineFunction &MF) const;
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bool reversePredSense(MachineInstr &MI) const;
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unsigned reversePrediction(unsigned Opcode) const;
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bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
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void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const;
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bool getBundleNoShuf(const MachineInstr &MIB) const;
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// Addressing mode relations.
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short changeAddrMode_abs_io(short Opc) const;
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short changeAddrMode_io_abs(short Opc) const;
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short changeAddrMode_io_pi(short Opc) const;
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short changeAddrMode_io_rr(short Opc) const;
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short changeAddrMode_pi_io(short Opc) const;
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short changeAddrMode_rr_io(short Opc) const;
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short changeAddrMode_rr_ur(short Opc) const;
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short changeAddrMode_ur_rr(short Opc) const;
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|
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short changeAddrMode_abs_io(const MachineInstr &MI) const {
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return changeAddrMode_abs_io(MI.getOpcode());
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}
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short changeAddrMode_io_abs(const MachineInstr &MI) const {
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return changeAddrMode_io_abs(MI.getOpcode());
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|
}
|
|
short changeAddrMode_io_rr(const MachineInstr &MI) const {
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|
return changeAddrMode_io_rr(MI.getOpcode());
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}
|
|
short changeAddrMode_rr_io(const MachineInstr &MI) const {
|
|
return changeAddrMode_rr_io(MI.getOpcode());
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|
}
|
|
short changeAddrMode_rr_ur(const MachineInstr &MI) const {
|
|
return changeAddrMode_rr_ur(MI.getOpcode());
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|
}
|
|
short changeAddrMode_ur_rr(const MachineInstr &MI) const {
|
|
return changeAddrMode_ur_rr(MI.getOpcode());
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}
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|
};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
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