forked from OSchip/llvm-project
88 lines
1.9 KiB
LLVM
88 lines
1.9 KiB
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
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; Make sure that the assembler mapped compare instructions are correctly generated.
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@c = common global i32 0, align 4
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define i32 @test1(i32 %a, i32 %b) nounwind {
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; CHECK-NOT: cmp.ge
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; CHECK: cmp.gt
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entry:
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%cmp = icmp slt i32 %a, 100
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br i1 %cmp, label %if.then, label %entry.if.end_crit_edge
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entry.if.end_crit_edge:
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%.pre = load i32* @c, align 4
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br label %if.end
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if.then:
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%sub = add nsw i32 %a, -10
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store i32 %sub, i32* @c, align 4
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br label %if.end
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if.end:
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%0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ]
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ret i32 %0
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}
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define i32 @test2(i32 %a, i32 %b) nounwind {
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; CHECK-NOT: cmp.lt
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; CHECK: cmp.gt
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entry:
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%cmp = icmp sge i32 %a, %b
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br i1 %cmp, label %entry.if.end_crit_edge, label %if.then
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entry.if.end_crit_edge:
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%.pre = load i32* @c, align 4
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br label %if.end
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if.then:
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%sub = add nsw i32 %a, -10
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store i32 %sub, i32* @c, align 4
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br label %if.end
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if.end:
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%0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ]
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ret i32 %0
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}
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define i32 @test4(i32 %a, i32 %b) nounwind {
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; CHECK-NOT: cmp.ltu
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; CHECK: cmp.gtu
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entry:
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%cmp = icmp uge i32 %a, %b
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br i1 %cmp, label %entry.if.end_crit_edge, label %if.then
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entry.if.end_crit_edge:
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%.pre = load i32* @c, align 4
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br label %if.end
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if.then:
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%sub = add i32 %a, -10
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store i32 %sub, i32* @c, align 4
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br label %if.end
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if.end:
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%0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ]
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ret i32 %0
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}
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define i32 @test5(i32 %a, i32 %b) nounwind {
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; CHECK: cmp.gtu
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entry:
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%cmp = icmp uge i32 %a, 29999
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br i1 %cmp, label %if.then, label %entry.if.end_crit_edge
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entry.if.end_crit_edge:
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%.pre = load i32* @c, align 4
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br label %if.end
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if.then:
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%sub = add i32 %a, -10
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store i32 %sub, i32* @c, align 4
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br label %if.end
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if.end:
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%0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ]
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ret i32 %0
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}
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