forked from OSchip/llvm-project
278 lines
11 KiB
LLVM
278 lines
11 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-machineinstrs | FileCheck %s
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;
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; Verify that misched resource/latency balancy heuristics are sane.
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define void @unrolled_mmult1(i32* %tmp55, i32* %tmp56, i32* %pre, i32* %pre94,
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i32* %pre95, i32* %pre96, i32* %pre97, i32* %pre98, i32* %pre99,
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i32* %pre100, i32* %pre101, i32* %pre102, i32* %pre103, i32* %pre104)
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nounwind uwtable ssp {
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entry:
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br label %for.body
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; imull folded loads should be in order and interleaved with addl, never
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; adjacent. Also check that we have no spilling.
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;
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; Since mmult1 IR is already in good order, this effectively ensure
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; the scheduler maintains source order.
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;
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; CHECK: %for.body
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; CHECK-NOT: %rsp
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; CHECK: imull 4
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 8
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 12
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 16
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 20
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 24
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 28
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 32
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 36
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: %end
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for.body:
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%indvars.iv42.i = phi i64 [ %indvars.iv.next43.i, %for.body ], [ 0, %entry ]
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%tmp57 = load i32* %tmp56, align 4
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%arrayidx12.us.i61 = getelementptr inbounds i32* %pre, i64 %indvars.iv42.i
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%tmp58 = load i32* %arrayidx12.us.i61, align 4
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%mul.us.i = mul nsw i32 %tmp58, %tmp57
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%arrayidx8.us.i.1 = getelementptr inbounds i32* %tmp56, i64 1
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%tmp59 = load i32* %arrayidx8.us.i.1, align 4
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%arrayidx12.us.i61.1 = getelementptr inbounds i32* %pre94, i64 %indvars.iv42.i
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%tmp60 = load i32* %arrayidx12.us.i61.1, align 4
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%mul.us.i.1 = mul nsw i32 %tmp60, %tmp59
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%add.us.i.1 = add nsw i32 %mul.us.i.1, %mul.us.i
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%arrayidx8.us.i.2 = getelementptr inbounds i32* %tmp56, i64 2
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%tmp61 = load i32* %arrayidx8.us.i.2, align 4
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%arrayidx12.us.i61.2 = getelementptr inbounds i32* %pre95, i64 %indvars.iv42.i
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%tmp62 = load i32* %arrayidx12.us.i61.2, align 4
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%mul.us.i.2 = mul nsw i32 %tmp62, %tmp61
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%add.us.i.2 = add nsw i32 %mul.us.i.2, %add.us.i.1
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%arrayidx8.us.i.3 = getelementptr inbounds i32* %tmp56, i64 3
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%tmp63 = load i32* %arrayidx8.us.i.3, align 4
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%arrayidx12.us.i61.3 = getelementptr inbounds i32* %pre96, i64 %indvars.iv42.i
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%tmp64 = load i32* %arrayidx12.us.i61.3, align 4
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%mul.us.i.3 = mul nsw i32 %tmp64, %tmp63
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%add.us.i.3 = add nsw i32 %mul.us.i.3, %add.us.i.2
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%arrayidx8.us.i.4 = getelementptr inbounds i32* %tmp56, i64 4
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%tmp65 = load i32* %arrayidx8.us.i.4, align 4
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%arrayidx12.us.i61.4 = getelementptr inbounds i32* %pre97, i64 %indvars.iv42.i
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%tmp66 = load i32* %arrayidx12.us.i61.4, align 4
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%mul.us.i.4 = mul nsw i32 %tmp66, %tmp65
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%add.us.i.4 = add nsw i32 %mul.us.i.4, %add.us.i.3
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%arrayidx8.us.i.5 = getelementptr inbounds i32* %tmp56, i64 5
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%tmp67 = load i32* %arrayidx8.us.i.5, align 4
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%arrayidx12.us.i61.5 = getelementptr inbounds i32* %pre98, i64 %indvars.iv42.i
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%tmp68 = load i32* %arrayidx12.us.i61.5, align 4
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%mul.us.i.5 = mul nsw i32 %tmp68, %tmp67
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%add.us.i.5 = add nsw i32 %mul.us.i.5, %add.us.i.4
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%arrayidx8.us.i.6 = getelementptr inbounds i32* %tmp56, i64 6
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%tmp69 = load i32* %arrayidx8.us.i.6, align 4
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%arrayidx12.us.i61.6 = getelementptr inbounds i32* %pre99, i64 %indvars.iv42.i
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%tmp70 = load i32* %arrayidx12.us.i61.6, align 4
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%mul.us.i.6 = mul nsw i32 %tmp70, %tmp69
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%add.us.i.6 = add nsw i32 %mul.us.i.6, %add.us.i.5
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%arrayidx8.us.i.7 = getelementptr inbounds i32* %tmp56, i64 7
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%tmp71 = load i32* %arrayidx8.us.i.7, align 4
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%arrayidx12.us.i61.7 = getelementptr inbounds i32* %pre100, i64 %indvars.iv42.i
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%tmp72 = load i32* %arrayidx12.us.i61.7, align 4
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%mul.us.i.7 = mul nsw i32 %tmp72, %tmp71
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%add.us.i.7 = add nsw i32 %mul.us.i.7, %add.us.i.6
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%arrayidx8.us.i.8 = getelementptr inbounds i32* %tmp56, i64 8
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%tmp73 = load i32* %arrayidx8.us.i.8, align 4
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%arrayidx12.us.i61.8 = getelementptr inbounds i32* %pre101, i64 %indvars.iv42.i
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%tmp74 = load i32* %arrayidx12.us.i61.8, align 4
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%mul.us.i.8 = mul nsw i32 %tmp74, %tmp73
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%add.us.i.8 = add nsw i32 %mul.us.i.8, %add.us.i.7
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%arrayidx8.us.i.9 = getelementptr inbounds i32* %tmp56, i64 9
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%tmp75 = load i32* %arrayidx8.us.i.9, align 4
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%arrayidx12.us.i61.9 = getelementptr inbounds i32* %pre102, i64 %indvars.iv42.i
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%tmp76 = load i32* %arrayidx12.us.i61.9, align 4
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%mul.us.i.9 = mul nsw i32 %tmp76, %tmp75
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%add.us.i.9 = add nsw i32 %mul.us.i.9, %add.us.i.8
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%arrayidx16.us.i = getelementptr inbounds i32* %tmp55, i64 %indvars.iv42.i
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store i32 %add.us.i.9, i32* %arrayidx16.us.i, align 4
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%indvars.iv.next43.i = add i64 %indvars.iv42.i, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next43.i to i32
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%exitcond = icmp eq i32 %lftr.wideiv, 10
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br i1 %exitcond, label %end, label %for.body
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end:
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ret void
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}
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; Unlike the above loop, this IR starts out bad and must be
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; rescheduled.
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;
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; CHECK: %for.body
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; CHECK-NOT: %rsp
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; CHECK: imull 4
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 8
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 12
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 16
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 20
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 24
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 28
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 32
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK: imull 36
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: addl
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; CHECK-NOT: {{imull|rsp}}
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; CHECK: %end
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define void @unrolled_mmult2(i32* %tmp55, i32* %tmp56, i32* %pre, i32* %pre94,
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i32* %pre95, i32* %pre96, i32* %pre97, i32* %pre98, i32* %pre99,
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i32* %pre100, i32* %pre101, i32* %pre102, i32* %pre103, i32* %pre104)
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nounwind uwtable ssp {
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entry:
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br label %for.body
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for.body:
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%indvars.iv42.i = phi i64 [ %indvars.iv.next43.i, %for.body ], [ 0, %entry ]
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%tmp57 = load i32* %tmp56, align 4
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%arrayidx12.us.i61 = getelementptr inbounds i32* %pre, i64 %indvars.iv42.i
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%tmp58 = load i32* %arrayidx12.us.i61, align 4
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%arrayidx8.us.i.1 = getelementptr inbounds i32* %tmp56, i64 1
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%tmp59 = load i32* %arrayidx8.us.i.1, align 4
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%arrayidx12.us.i61.1 = getelementptr inbounds i32* %pre94, i64 %indvars.iv42.i
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%tmp60 = load i32* %arrayidx12.us.i61.1, align 4
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%arrayidx8.us.i.2 = getelementptr inbounds i32* %tmp56, i64 2
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%tmp61 = load i32* %arrayidx8.us.i.2, align 4
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%arrayidx12.us.i61.2 = getelementptr inbounds i32* %pre95, i64 %indvars.iv42.i
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%tmp62 = load i32* %arrayidx12.us.i61.2, align 4
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%arrayidx8.us.i.3 = getelementptr inbounds i32* %tmp56, i64 3
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%tmp63 = load i32* %arrayidx8.us.i.3, align 4
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%arrayidx12.us.i61.3 = getelementptr inbounds i32* %pre96, i64 %indvars.iv42.i
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%tmp64 = load i32* %arrayidx12.us.i61.3, align 4
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%arrayidx8.us.i.4 = getelementptr inbounds i32* %tmp56, i64 4
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%tmp65 = load i32* %arrayidx8.us.i.4, align 4
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%arrayidx12.us.i61.4 = getelementptr inbounds i32* %pre97, i64 %indvars.iv42.i
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%tmp66 = load i32* %arrayidx12.us.i61.4, align 4
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%arrayidx8.us.i.5 = getelementptr inbounds i32* %tmp56, i64 5
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%tmp67 = load i32* %arrayidx8.us.i.5, align 4
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%arrayidx12.us.i61.5 = getelementptr inbounds i32* %pre98, i64 %indvars.iv42.i
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%tmp68 = load i32* %arrayidx12.us.i61.5, align 4
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%arrayidx8.us.i.6 = getelementptr inbounds i32* %tmp56, i64 6
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%tmp69 = load i32* %arrayidx8.us.i.6, align 4
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%arrayidx12.us.i61.6 = getelementptr inbounds i32* %pre99, i64 %indvars.iv42.i
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%tmp70 = load i32* %arrayidx12.us.i61.6, align 4
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%mul.us.i = mul nsw i32 %tmp58, %tmp57
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%arrayidx8.us.i.7 = getelementptr inbounds i32* %tmp56, i64 7
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%tmp71 = load i32* %arrayidx8.us.i.7, align 4
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%arrayidx12.us.i61.7 = getelementptr inbounds i32* %pre100, i64 %indvars.iv42.i
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%tmp72 = load i32* %arrayidx12.us.i61.7, align 4
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%arrayidx8.us.i.8 = getelementptr inbounds i32* %tmp56, i64 8
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%tmp73 = load i32* %arrayidx8.us.i.8, align 4
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%arrayidx12.us.i61.8 = getelementptr inbounds i32* %pre101, i64 %indvars.iv42.i
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%tmp74 = load i32* %arrayidx12.us.i61.8, align 4
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%arrayidx8.us.i.9 = getelementptr inbounds i32* %tmp56, i64 9
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%tmp75 = load i32* %arrayidx8.us.i.9, align 4
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%arrayidx12.us.i61.9 = getelementptr inbounds i32* %pre102, i64 %indvars.iv42.i
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%tmp76 = load i32* %arrayidx12.us.i61.9, align 4
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%mul.us.i.1 = mul nsw i32 %tmp60, %tmp59
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%add.us.i.1 = add nsw i32 %mul.us.i.1, %mul.us.i
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%mul.us.i.2 = mul nsw i32 %tmp62, %tmp61
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%add.us.i.2 = add nsw i32 %mul.us.i.2, %add.us.i.1
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%mul.us.i.3 = mul nsw i32 %tmp64, %tmp63
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%add.us.i.3 = add nsw i32 %mul.us.i.3, %add.us.i.2
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%mul.us.i.4 = mul nsw i32 %tmp66, %tmp65
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%add.us.i.4 = add nsw i32 %mul.us.i.4, %add.us.i.3
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%mul.us.i.5 = mul nsw i32 %tmp68, %tmp67
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%add.us.i.5 = add nsw i32 %mul.us.i.5, %add.us.i.4
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%mul.us.i.6 = mul nsw i32 %tmp70, %tmp69
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%add.us.i.6 = add nsw i32 %mul.us.i.6, %add.us.i.5
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%mul.us.i.7 = mul nsw i32 %tmp72, %tmp71
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%add.us.i.7 = add nsw i32 %mul.us.i.7, %add.us.i.6
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%mul.us.i.8 = mul nsw i32 %tmp74, %tmp73
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%add.us.i.8 = add nsw i32 %mul.us.i.8, %add.us.i.7
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%mul.us.i.9 = mul nsw i32 %tmp76, %tmp75
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%add.us.i.9 = add nsw i32 %mul.us.i.9, %add.us.i.8
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%arrayidx16.us.i = getelementptr inbounds i32* %tmp55, i64 %indvars.iv42.i
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store i32 %add.us.i.9, i32* %arrayidx16.us.i, align 4
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%indvars.iv.next43.i = add i64 %indvars.iv42.i, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next43.i to i32
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%exitcond = icmp eq i32 %lftr.wideiv, 10
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br i1 %exitcond, label %end, label %for.body
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end:
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ret void
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}
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; A mildly interesting little block extracted from a cipher. The
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; balanced heuristics are interesting here because we have resource,
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; latency, and register limits all at once. For now, simply check that
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; we don't use any callee-saves.
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; CHECK: @encpc1
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; CHECK: %entry
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; CHECK-NOT: push
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; CHECK-NOT: pop
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; CHECK: ret
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@a = external global i32, align 4
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@b = external global i32, align 4
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@c = external global i32, align 4
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@d = external global i32, align 4
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define i32 @encpc1() nounwind {
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entry:
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%l1 = load i32* @a, align 16
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%conv = shl i32 %l1, 8
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%s5 = lshr i32 %l1, 8
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%add = or i32 %conv, %s5
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store i32 %add, i32* @b
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%l6 = load i32* @a
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%l7 = load i32* @c
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%add.i = add i32 %l7, %l6
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%idxprom.i = zext i32 %l7 to i64
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%arrayidx.i = getelementptr inbounds i32* @d, i64 %idxprom.i
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%l8 = load i32* %arrayidx.i
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store i32 346, i32* @c
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store i32 20021, i32* @d
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%l9 = load i32* @a
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store i32 %l8, i32* @a
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store i32 %l9, i32* @b
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store i32 %add.i, i32* @c
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store i32 %l9, i32* @d
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%cmp.i = icmp eq i32 %add.i, 0
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%s10 = lshr i32 %l1, 16
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%s12 = lshr i32 %l1, 24
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%s14 = lshr i32 %l1, 30
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br i1 %cmp.i, label %if, label %return
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if:
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%sa = add i32 %s5, %s10
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%sb = add i32 %sa, %s12
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%sc = add i32 %sb, %s14
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br label %return
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return:
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%result = phi i32 [0, %entry], [%sc, %if]
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ret i32 %result
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}
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