forked from OSchip/llvm-project
				
			
		
			
				
	
	
		
			144 lines
		
	
	
		
			4.8 KiB
		
	
	
	
		
			C++
		
	
	
	
			
		
		
	
	
			144 lines
		
	
	
		
			4.8 KiB
		
	
	
	
		
			C++
		
	
	
	
| //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
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| //
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| //                     The LLVM Compiler Infrastructure
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| //
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| // This file is distributed under the University of Illinois Open Source
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| // License. See LICENSE.TXT for details.
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| //
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| //===----------------------------------------------------------------------===//
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| //
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| // This file declares the ARM specific subclass of TargetMachine.
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| //
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| //===----------------------------------------------------------------------===//
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| 
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| #ifndef ARMTARGETMACHINE_H
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| #define ARMTARGETMACHINE_H
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| 
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| #include "ARMInstrInfo.h"
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| #include "ARMELFWriterInfo.h"
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| #include "ARMFrameLowering.h"
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| #include "ARMJITInfo.h"
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| #include "ARMSubtarget.h"
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| #include "ARMISelLowering.h"
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| #include "ARMSelectionDAGInfo.h"
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| #include "Thumb1InstrInfo.h"
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| #include "Thumb1FrameLowering.h"
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| #include "Thumb2InstrInfo.h"
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| #include "llvm/Target/TargetMachine.h"
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| #include "llvm/Target/TargetData.h"
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| #include "llvm/MC/MCStreamer.h"
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| #include "llvm/ADT/OwningPtr.h"
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| 
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| namespace llvm {
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| 
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| class ARMBaseTargetMachine : public LLVMTargetMachine {
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| protected:
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|   ARMSubtarget        Subtarget;
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| private:
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|   ARMJITInfo          JITInfo;
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|   InstrItineraryData  InstrItins;
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|   Reloc::Model        DefRelocModel;    // Reloc model before it's overridden.
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| 
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| public:
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|   ARMBaseTargetMachine(const Target &T, const std::string &TT,
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|                        const std::string &FS, bool isThumb);
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| 
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|   virtual       ARMJITInfo       *getJITInfo()         { return &JITInfo; }
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|   virtual const ARMSubtarget  *getSubtargetImpl() const { return &Subtarget; }
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|   virtual const InstrItineraryData *getInstrItineraryData() const {
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|     return &InstrItins;
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|   }
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| 
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|   // Pass Pipeline Configuration
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|   virtual bool addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
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|   virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
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|   virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
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|   virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
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|   virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
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|   virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
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|                               JITCodeEmitter &MCE);
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| };
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| 
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| /// ARMTargetMachine - ARM target machine.
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| ///
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| class ARMTargetMachine : public ARMBaseTargetMachine {
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|   ARMInstrInfo        InstrInfo;
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|   const TargetData    DataLayout;       // Calculates type size & alignment
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|   ARMELFWriterInfo    ELFWriterInfo;
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|   ARMTargetLowering   TLInfo;
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|   ARMSelectionDAGInfo TSInfo;
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|   ARMFrameLowering    FrameLowering;
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|  public:
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|   ARMTargetMachine(const Target &T, const std::string &TT,
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|                    const std::string &FS);
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| 
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|   virtual const ARMRegisterInfo  *getRegisterInfo() const {
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|     return &InstrInfo.getRegisterInfo();
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|   }
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| 
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|   virtual const ARMTargetLowering *getTargetLowering() const {
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|     return &TLInfo;
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|   }
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| 
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|   virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
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|     return &TSInfo;
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|   }
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|   virtual const ARMFrameLowering *getFrameLowering() const {
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|     return &FrameLowering;
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|   }
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| 
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|   virtual const ARMInstrInfo     *getInstrInfo() const { return &InstrInfo; }
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|   virtual const TargetData       *getTargetData() const { return &DataLayout; }
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|   virtual const ARMELFWriterInfo *getELFWriterInfo() const {
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|     return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
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|   }
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| };
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| 
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| /// ThumbTargetMachine - Thumb target machine.
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| /// Due to the way architectures are handled, this represents both
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| ///   Thumb-1 and Thumb-2.
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| ///
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| class ThumbTargetMachine : public ARMBaseTargetMachine {
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|   // Either Thumb1InstrInfo or Thumb2InstrInfo.
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|   OwningPtr<ARMBaseInstrInfo> InstrInfo;
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|   const TargetData    DataLayout;   // Calculates type size & alignment
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|   ARMELFWriterInfo    ELFWriterInfo;
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|   ARMTargetLowering   TLInfo;
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|   ARMSelectionDAGInfo TSInfo;
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|   // Either Thumb1FrameLowering or ARMFrameLowering.
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|   OwningPtr<ARMFrameLowering> FrameLowering;
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| public:
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|   ThumbTargetMachine(const Target &T, const std::string &TT,
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|                      const std::string &FS);
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| 
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|   /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
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|   virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
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|     return &InstrInfo->getRegisterInfo();
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|   }
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| 
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|   virtual const ARMTargetLowering *getTargetLowering() const {
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|     return &TLInfo;
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|   }
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| 
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|   virtual const ARMSelectionDAGInfo *getSelectionDAGInfo() const {
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|     return &TSInfo;
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|   }
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| 
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|   /// returns either Thumb1InstrInfo or Thumb2InstrInfo
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|   virtual const ARMBaseInstrInfo *getInstrInfo() const {
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|     return InstrInfo.get();
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|   }
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|   /// returns either Thumb1FrameLowering or ARMFrameLowering
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|   virtual const ARMFrameLowering *getFrameLowering() const {
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|     return FrameLowering.get();
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|   }
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|   virtual const TargetData       *getTargetData() const { return &DataLayout; }
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|   virtual const ARMELFWriterInfo *getELFWriterInfo() const {
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|     return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
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|   }
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| };
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| 
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| } // end namespace llvm
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| 
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| #endif
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