forked from OSchip/llvm-project
377 lines
12 KiB
C++
377 lines
12 KiB
C++
//===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the X86 specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "subtarget"
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#include "X86Subtarget.h"
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#include "X86InstrInfo.h"
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#include "X86GenSubtarget.inc"
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#include "llvm/GlobalValue.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/Host.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/SmallVector.h"
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using namespace llvm;
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#if defined(_MSC_VER)
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#include <intrin.h>
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#endif
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/// ClassifyBlockAddressReference - Classify a blockaddress reference for the
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/// current subtarget according to how we should reference it in a non-pcrel
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/// context.
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unsigned char X86Subtarget::
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ClassifyBlockAddressReference() const {
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if (isPICStyleGOT()) // 32-bit ELF targets.
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return X86II::MO_GOTOFF;
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if (isPICStyleStubPIC()) // Darwin/32 in PIC mode.
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return X86II::MO_PIC_BASE_OFFSET;
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// Direct static reference to label.
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return X86II::MO_NO_FLAG;
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}
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/// ClassifyGlobalReference - Classify a global variable reference for the
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/// current subtarget according to how we should reference it in a non-pcrel
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/// context.
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unsigned char X86Subtarget::
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ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
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// DLLImport only exists on windows, it is implemented as a load from a
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// DLLIMPORT stub.
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if (GV->hasDLLImportLinkage())
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return X86II::MO_DLLIMPORT;
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// Determine whether this is a reference to a definition or a declaration.
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// Materializable GVs (in JIT lazy compilation mode) do not require an extra
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// load from stub.
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bool isDecl = GV->hasAvailableExternallyLinkage();
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if (GV->isDeclaration() && !GV->isMaterializable())
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isDecl = true;
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// X86-64 in PIC mode.
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if (isPICStyleRIPRel()) {
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// Large model never uses stubs.
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if (TM.getCodeModel() == CodeModel::Large)
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return X86II::MO_NO_FLAG;
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if (isTargetDarwin()) {
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// If symbol visibility is hidden, the extra load is not needed if
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// target is x86-64 or the symbol is definitely defined in the current
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// translation unit.
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if (GV->hasDefaultVisibility() &&
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(isDecl || GV->isWeakForLinker()))
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return X86II::MO_GOTPCREL;
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} else if (!isTargetWin64()) {
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assert(isTargetELF() && "Unknown rip-relative target");
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// Extra load is needed for all externally visible.
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if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
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return X86II::MO_GOTPCREL;
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}
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return X86II::MO_NO_FLAG;
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}
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if (isPICStyleGOT()) { // 32-bit ELF targets.
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// Extra load is needed for all externally visible.
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if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
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return X86II::MO_GOTOFF;
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return X86II::MO_GOT;
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}
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if (isPICStyleStubPIC()) { // Darwin/32 in PIC mode.
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// Determine whether we have a stub reference and/or whether the reference
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// is relative to the PIC base or not.
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return X86II::MO_PIC_BASE_OFFSET;
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
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// If symbol visibility is hidden, we have a stub for common symbol
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// references and external declarations.
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if (isDecl || GV->hasCommonLinkage()) {
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// Hidden $non_lazy_ptr reference.
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return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
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}
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// Otherwise, no stub.
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return X86II::MO_PIC_BASE_OFFSET;
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}
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if (isPICStyleStubNoDynamic()) { // Darwin/32 in -mdynamic-no-pic mode.
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// Determine whether we have a stub reference.
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return X86II::MO_NO_FLAG;
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return X86II::MO_DARWIN_NONLAZY;
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// Otherwise, no stub.
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return X86II::MO_NO_FLAG;
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}
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// Direct static reference to global.
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return X86II::MO_NO_FLAG;
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}
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/// getBZeroEntry - This function returns the name of a function which has an
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/// interface like the non-standard bzero function, if such a function exists on
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/// the current subtarget and it is considered prefereable over memset with zero
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/// passed as the second argument. Otherwise it returns null.
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const char *X86Subtarget::getBZeroEntry() const {
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// Darwin 10 has a __bzero entry point for this purpose.
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if (getDarwinVers() >= 10)
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return "__bzero";
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return 0;
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}
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/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
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/// to immediate address.
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bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
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if (Is64Bit)
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return false;
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return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
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}
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/// getSpecialAddressLatency - For targets where it is beneficial to
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/// backschedule instructions that compute addresses, return a value
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/// indicating the number of scheduling cycles of backscheduling that
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/// should be attempted.
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unsigned X86Subtarget::getSpecialAddressLatency() const {
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// For x86 out-of-order targets, back-schedule address computations so
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// that loads and stores aren't blocked.
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// This value was chosen arbitrarily.
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return 200;
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}
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/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
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/// specified arguments. If we can't run cpuid on the host, return true.
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static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
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unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
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#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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#if defined(__GNUC__)
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// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
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asm ("movq\t%%rbx, %%rsi\n\t"
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"cpuid\n\t"
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"xchgq\t%%rbx, %%rsi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#elif defined(_MSC_VER)
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int registers[4];
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__cpuid(registers, value);
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*rEAX = registers[0];
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*rEBX = registers[1];
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*rECX = registers[2];
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*rEDX = registers[3];
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return false;
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#endif
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#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
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#if defined(__GNUC__)
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asm ("movl\t%%ebx, %%esi\n\t"
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"cpuid\n\t"
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"xchgl\t%%ebx, %%esi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#elif defined(_MSC_VER)
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__asm {
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mov eax,value
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cpuid
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mov esi,rEAX
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mov dword ptr [esi],eax
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mov esi,rEBX
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mov dword ptr [esi],ebx
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mov esi,rECX
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mov dword ptr [esi],ecx
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mov esi,rEDX
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mov dword ptr [esi],edx
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}
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return false;
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#endif
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#endif
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return true;
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}
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static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
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Family = (EAX >> 8) & 0xf; // Bits 8 - 11
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Model = (EAX >> 4) & 0xf; // Bits 4 - 7
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if (Family == 6 || Family == 0xf) {
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if (Family == 0xf)
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// Examine extended family ID if family ID is F.
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Family += (EAX >> 20) & 0xff; // Bits 20 - 27
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// Examine extended model ID if family ID is 6 or F.
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Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
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}
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}
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void X86Subtarget::AutoDetectSubtargetFeatures() {
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unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
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union {
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unsigned u[3];
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char c[12];
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} text;
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if (GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
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return;
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GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
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if ((EDX >> 15) & 1) HasCMov = true;
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if ((EDX >> 23) & 1) X86SSELevel = MMX;
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if ((EDX >> 25) & 1) X86SSELevel = SSE1;
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if ((EDX >> 26) & 1) X86SSELevel = SSE2;
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if (ECX & 0x1) X86SSELevel = SSE3;
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if ((ECX >> 9) & 1) X86SSELevel = SSSE3;
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if ((ECX >> 19) & 1) X86SSELevel = SSE41;
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if ((ECX >> 20) & 1) X86SSELevel = SSE42;
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// FIXME: AVX codegen support is not ready.
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//if ((ECX >> 28) & 1) { HasAVX = true; X86SSELevel = NoMMXSSE; }
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bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
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bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
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HasCLMUL = IsIntel && ((ECX >> 1) & 0x1);
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HasFMA3 = IsIntel && ((ECX >> 12) & 0x1);
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HasAES = IsIntel && ((ECX >> 25) & 0x1);
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if (IsIntel || IsAMD) {
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// Determine if bit test memory instructions are slow.
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unsigned Family = 0;
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unsigned Model = 0;
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DetectFamilyModel(EAX, Family, Model);
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IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
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// If it's Nehalem, unaligned memory access is fast.
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if (Family == 15 && Model == 26)
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IsUAMemFast = true;
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GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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HasX86_64 = (EDX >> 29) & 0x1;
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HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
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HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
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}
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}
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X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS,
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bool is64Bit)
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: PICStyle(PICStyles::None)
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, X86SSELevel(NoMMXSSE)
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, X863DNowLevel(NoThreeDNow)
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, HasCMov(false)
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, HasX86_64(false)
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, HasPOPCNT(false)
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, HasSSE4A(false)
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, HasAVX(false)
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, HasAES(false)
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, HasCLMUL(false)
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, HasFMA3(false)
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, HasFMA4(false)
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, IsBTMemSlow(false)
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, IsUAMemFast(false)
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, HasVectorUAMem(false)
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, stackAlignment(8)
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// FIXME: this is a known good value for Yonah. How about others?
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, MaxInlineSizeThreshold(128)
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, TargetTriple(TT)
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, Is64Bit(is64Bit) {
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// default to hard float ABI
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if (FloatABIType == FloatABI::Default)
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FloatABIType = FloatABI::Hard;
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// Determine default and user specified characteristics
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if (!FS.empty()) {
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// If feature string is not empty, parse features string.
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std::string CPU = sys::getHostCPUName();
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ParseSubtargetFeatures(FS, CPU);
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// All X86-64 CPUs also have SSE2, however user might request no SSE via
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// -mattr, so don't force SSELevel here.
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if (HasAVX)
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X86SSELevel = NoMMXSSE;
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} else {
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// Otherwise, use CPUID to auto-detect feature set.
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AutoDetectSubtargetFeatures();
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// Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
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if (Is64Bit && !HasAVX && X86SSELevel < SSE2)
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X86SSELevel = SSE2;
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}
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// If requesting codegen for X86-64, make sure that 64-bit features
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// are enabled.
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if (Is64Bit) {
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HasX86_64 = true;
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// All 64-bit cpus have cmov support.
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HasCMov = true;
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}
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DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
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<< ", 3DNowLevel " << X863DNowLevel
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<< ", 64bit " << HasX86_64 << "\n");
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assert((!Is64Bit || HasX86_64) &&
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"64-bit code requested on a subtarget that doesn't support it!");
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// Stack alignment is 16 bytes on Darwin, FreeBSD, Linux and Solaris (both
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// 32 and 64 bit) and for all 64-bit targets.
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if (isTargetDarwin() || isTargetFreeBSD() || isTargetLinux() ||
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isTargetSolaris() || Is64Bit)
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stackAlignment = 16;
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if (StackAlignment)
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stackAlignment = StackAlignment;
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}
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/// IsCalleePop - Determines whether the callee is required to pop its
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/// own arguments. Callee pop is necessary to support tail calls.
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bool X86Subtarget::IsCalleePop(bool IsVarArg,
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CallingConv::ID CallingConv) const {
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if (IsVarArg)
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return false;
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switch (CallingConv) {
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default:
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return false;
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case CallingConv::X86_StdCall:
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return !is64Bit();
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case CallingConv::X86_FastCall:
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return !is64Bit();
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case CallingConv::X86_ThisCall:
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return !is64Bit();
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case CallingConv::Fast:
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return GuaranteedTailCallOpt;
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case CallingConv::GHC:
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return GuaranteedTailCallOpt;
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}
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}
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