forked from OSchip/llvm-project
95ac3d15e9
For some reductions like G_VECREDUCE_OR on AArch64, we need to scalarize completely if the source is <= 64b. This change adds support for that in the legalizer. If the source has a pow-2 num elements, then we can do a tree reduction using the scalar operation in the individual elements. Otherwise, we just create a sequential chain of operations. For AArch64, we only need to scalarize if the input is <64b. If it's great than 64b then we can first do a fewElements step to 64b, taking advantage of vector instructions until we reach the point of scalarization. I also had to relax the verifier checks for reductions because the intrinsics support <1 x EltTy> types, which we lower to scalars for GlobalISel. Differential Revision: https://reviews.llvm.org/D108276 |
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| .. | ||
| CMakeLists.txt | ||
| CSEInfo.cpp | ||
| CSEMIRBuilder.cpp | ||
| CallLowering.cpp | ||
| Combiner.cpp | ||
| CombinerHelper.cpp | ||
| GISelChangeObserver.cpp | ||
| GISelKnownBits.cpp | ||
| GlobalISel.cpp | ||
| IRTranslator.cpp | ||
| InlineAsmLowering.cpp | ||
| InstructionSelect.cpp | ||
| InstructionSelector.cpp | ||
| LegacyLegalizerInfo.cpp | ||
| LegalityPredicates.cpp | ||
| LegalizeMutations.cpp | ||
| Legalizer.cpp | ||
| LegalizerHelper.cpp | ||
| LegalizerInfo.cpp | ||
| Localizer.cpp | ||
| LostDebugLocObserver.cpp | ||
| MachineIRBuilder.cpp | ||
| RegBankSelect.cpp | ||
| RegisterBank.cpp | ||
| RegisterBankInfo.cpp | ||
| Utils.cpp | ||