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AArch64
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[AArch64InstPrinter] Change printAlignedLabel to print the target address in hexadecimal form
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2020-04-10 09:21:09 -07:00 |
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AMDGPU
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[AMDGPU] Disable sub-dword scralar loads IR widening
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2020-04-10 08:20:49 -07:00 |
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ARC
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…
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ARM
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Re-land [Codegen/Statepoint] Allow usage of registers for non gc deopt values.
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2020-04-10 10:13:39 +07:00 |
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AVR
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[AVR] Generalize the previous interrupt bugfix to signal handlers too
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2020-03-31 19:33:34 +13:00 |
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BPF
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[llvm] Fix missing FileCheck directive colons
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2020-04-06 09:59:08 -06:00 |
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Generic
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Add pass to strip debug info from MIR
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2020-04-09 15:44:38 -07:00 |
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Hexagon
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[llvm] Fix missing FileCheck directive colons
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2020-04-06 09:59:08 -06:00 |
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Inputs
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…
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Lanai
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…
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MIR
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AMDGPU: Assume f32 denormals are enabled by default
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2020-04-02 17:17:12 -04:00 |
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MSP430
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…
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Mips
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[llvm] Fix missing FileCheck directive colons
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2020-04-06 09:59:08 -06:00 |
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NVPTX
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[llvm] Fix missing FileCheck directive colons
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2020-04-06 09:59:08 -06:00 |
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PowerPC
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[PowerPC][NFC] Add test for 5b18b6e9a8
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2020-04-10 11:41:03 -05:00 |
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RISCV
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[LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG
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2020-04-01 15:51:26 +01:00 |
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SPARC
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…
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SystemZ
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[LoopDataPrefetch + SystemZ] Let target decide on prefetching for each loop.
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2020-04-02 14:57:46 +02:00 |
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Thumb
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[ARM] unwinding .pad instructions missing in execute-only prologue
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2020-04-07 11:51:59 +01:00 |
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Thumb2
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[ARM][MVE] Optimise offset addresses of gathers/scatters
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2020-04-08 11:46:57 +01:00 |
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VE
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[VE] Support (m)0 and (m)1 operands
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2020-04-09 18:09:00 +02:00 |
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WebAssembly
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[WebAssembly] Use dummy debug info in Emscripten SjLj
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2020-04-09 18:44:50 -07:00 |
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WinCFGuard
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…
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WinEH
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…
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X86
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Re-land [Codegen/Statepoint] Allow usage of registers for non gc deopt values.
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2020-04-10 10:13:39 +07:00 |
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XCore
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…
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