forked from OSchip/llvm-project
125 lines
4.9 KiB
C++
125 lines
4.9 KiB
C++
//===-- Mips16InstrInfo.h - Mips16 Instruction Information ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips16 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPS16INSTRUCTIONINFO_H
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#define MIPS16INSTRUCTIONINFO_H
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#include "Mips16RegisterInfo.h"
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#include "MipsInstrInfo.h"
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namespace llvm {
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class Mips16InstrInfo : public MipsInstrInfo {
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const Mips16RegisterInfo RI;
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public:
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explicit Mips16InstrInfo(MipsTargetMachine &TM);
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virtual const MipsRegisterInfo &getRegisterInfo() const;
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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virtual void storeRegToStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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int64_t Offset) const;
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virtual void loadRegFromStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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int64_t Offset) const;
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virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
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virtual unsigned getOppositeBranchOpc(unsigned Opc) const;
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// Adjust SP by FrameSize bytes. Save RA, S0, S1
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void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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// Adjust SP by FrameSize bytes. Restore RA, S0, S1
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void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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/// Adjust SP by Amount bytes.
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void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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/// Emit a series of instructions to load an immediate.
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// This is to adjust some FrameReg. We return the new register to be used
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// in place of FrameReg and the adjusted immediate field (&NewImm)
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//
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unsigned loadImmediate(unsigned FrameReg,
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int64_t Imm, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, DebugLoc DL,
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unsigned &NewImm) const;
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static bool validSpImm8(int offset) {
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return ((offset & 7) == 0) && isInt<11>(offset);
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}
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//
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// build the proper one based on the Imm field
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//
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const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
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void BuildAddiuSpImm
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(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
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private:
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virtual unsigned getAnalyzableBrOpc(unsigned Opc) const;
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void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned Opc) const;
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// Adjust SP by Amount bytes where bytes can be up to 32bit number.
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void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned Reg1, unsigned Reg2) const;
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// Adjust SP by Amount bytes where bytes can be up to 32bit number.
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void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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};
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}
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#endif
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