forked from OSchip/llvm-project
101 lines
3.5 KiB
C++
101 lines
3.5 KiB
C++
//===-- TargetSubtargetInfo.cpp - General Target Information ---------------==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file describes the general parts of a Subtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/TargetSchedule.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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//---------------------------------------------------------------------------
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// TargetSubtargetInfo Class
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//
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TargetSubtargetInfo::TargetSubtargetInfo(
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const Triple &TT, StringRef CPU, StringRef FS,
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ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
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const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
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const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
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const InstrStage *IS, const unsigned *OC, const unsigned *FP)
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: MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
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}
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TargetSubtargetInfo::~TargetSubtargetInfo() {}
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bool TargetSubtargetInfo::enableAtomicExpand() const {
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return true;
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}
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bool TargetSubtargetInfo::enableMachineScheduler() const {
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return false;
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}
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bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
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return enableMachineScheduler();
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}
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bool TargetSubtargetInfo::enableRALocalReassignment(
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CodeGenOpt::Level OptLevel) const {
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return true;
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}
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bool TargetSubtargetInfo::enablePostRAScheduler() const {
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return getSchedModel().PostRAScheduler;
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}
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bool TargetSubtargetInfo::useAA() const {
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return false;
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}
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static std::string createSchedInfoStr(unsigned Latency,
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Optional<double> RThroughput) {
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static const char *SchedPrefix = " sched: [";
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std::string Comment;
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raw_string_ostream CS(Comment);
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if (Latency > 0 && RThroughput.hasValue())
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CS << SchedPrefix << Latency << format(":%2.2f", RThroughput.getValue())
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<< "]";
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else if (Latency > 0)
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CS << SchedPrefix << Latency << ":?]";
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else if (RThroughput.hasValue())
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CS << SchedPrefix << "?:" << RThroughput.getValue() << "]";
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CS.flush();
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return Comment;
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}
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/// Returns string representation of scheduler comment
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std::string TargetSubtargetInfo::getSchedInfoStr(const MachineInstr &MI) const {
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if (MI.isPseudo() || MI.isTerminator())
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return std::string();
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// We don't cache TSchedModel because it depends on TargetInstrInfo
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// that could be changed during the compilation
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TargetSchedModel TSchedModel;
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TSchedModel.init(getSchedModel(), this, getInstrInfo());
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unsigned Latency = TSchedModel.computeInstrLatency(&MI);
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Optional<double> RThroughput = TSchedModel.computeInstrRThroughput(&MI);
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return createSchedInfoStr(Latency, RThroughput);
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}
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/// Returns string representation of scheduler comment
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std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const {
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// We don't cache TSchedModel because it depends on TargetInstrInfo
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// that could be changed during the compilation
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TargetSchedModel TSchedModel;
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TSchedModel.init(getSchedModel(), this, getInstrInfo());
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if (!TSchedModel.hasInstrSchedModel())
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return std::string();
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unsigned Latency = TSchedModel.computeInstrLatency(MCI.getOpcode());
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Optional<double> RThroughput =
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TSchedModel.computeInstrRThroughput(MCI.getOpcode());
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return createSchedInfoStr(Latency, RThroughput);
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}
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