forked from OSchip/llvm-project
149 lines
3.9 KiB
C++
149 lines
3.9 KiB
C++
//===-- AVRRelaxMemOperations.cpp - Relax out of range loads/stores -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass which relaxes out of range memory operations into
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// equivalent operations which handle bigger addresses.
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//
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//===----------------------------------------------------------------------===//
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#include "AVR.h"
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#include "AVRInstrInfo.h"
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#include "AVRTargetMachine.h"
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#include "MCTargetDesc/AVRMCTargetDesc.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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using namespace llvm;
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#define AVR_RELAX_MEM_OPS_NAME "AVR memory operation relaxation pass"
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namespace {
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class AVRRelaxMem : public MachineFunctionPass {
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public:
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static char ID;
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AVRRelaxMem() : MachineFunctionPass(ID) {
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initializeAVRRelaxMemPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return AVR_RELAX_MEM_OPS_NAME; }
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private:
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typedef MachineBasicBlock Block;
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typedef Block::iterator BlockIt;
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const TargetInstrInfo *TII;
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template <unsigned OP> bool relax(Block &MBB, BlockIt MBBI);
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bool runOnBasicBlock(Block &MBB);
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bool runOnInstruction(Block &MBB, BlockIt MBBI);
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MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode) {
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return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
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}
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};
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char AVRRelaxMem::ID = 0;
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bool AVRRelaxMem::runOnMachineFunction(MachineFunction &MF) {
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bool Modified = false;
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const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
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TII = STI.getInstrInfo();
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for (Block &MBB : MF) {
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bool BlockModified = runOnBasicBlock(MBB);
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Modified |= BlockModified;
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}
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return Modified;
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}
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bool AVRRelaxMem::runOnBasicBlock(Block &MBB) {
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bool Modified = false;
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BlockIt MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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BlockIt NMBBI = std::next(MBBI);
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Modified |= runOnInstruction(MBB, MBBI);
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MBBI = NMBBI;
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}
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return Modified;
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}
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template <>
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bool AVRRelaxMem::relax<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
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MachineInstr &MI = *MBBI;
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MachineOperand &Ptr = MI.getOperand(0);
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MachineOperand &Src = MI.getOperand(2);
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int64_t Imm = MI.getOperand(1).getImm();
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// We can definitely optimise this better.
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if (Imm > 63) {
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// Push the previous state of the pointer register.
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// This instruction must preserve the value.
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buildMI(MBB, MBBI, AVR::PUSHWRr)
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.addReg(Ptr.getReg());
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// Add the immediate to the pointer register.
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buildMI(MBB, MBBI, AVR::SBCIWRdK)
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.addReg(Ptr.getReg(), RegState::Define)
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.addReg(Ptr.getReg())
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.addImm(-Imm);
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// Store the value in the source register to the address
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// pointed to by the pointer register.
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buildMI(MBB, MBBI, AVR::STWPtrRr)
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.addReg(Ptr.getReg())
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.addReg(Src.getReg(), getKillRegState(Src.isKill()));
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// Pop the original state of the pointer register.
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buildMI(MBB, MBBI, AVR::POPWRd)
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.addReg(Ptr.getReg(), getKillRegState(Ptr.isKill()));
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MI.removeFromParent();
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}
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return false;
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}
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bool AVRRelaxMem::runOnInstruction(Block &MBB, BlockIt MBBI) {
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MachineInstr &MI = *MBBI;
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int Opcode = MBBI->getOpcode();
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#define RELAX(Op) \
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case Op: \
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return relax<Op>(MBB, MI)
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switch (Opcode) {
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RELAX(AVR::STDWPtrQRr);
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}
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#undef RELAX
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return false;
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}
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} // end of anonymous namespace
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INITIALIZE_PASS(AVRRelaxMem, "avr-relax-mem",
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AVR_RELAX_MEM_OPS_NAME, false, false)
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namespace llvm {
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FunctionPass *createAVRRelaxMemPass() { return new AVRRelaxMem(); }
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} // end of namespace llvm
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