forked from OSchip/llvm-project
277 lines
9.0 KiB
C++
277 lines
9.0 KiB
C++
//===- X86EvexToVex.cpp ---------------------------------------------------===//
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// Compress EVEX instructions to VEX encoding when possible to reduce code size
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file defines the pass that goes over all AVX-512 instructions which
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/// are encoded using the EVEX prefix and if possible replaces them by their
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/// corresponding VEX encoding which is usually shorter by 2 bytes.
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/// EVEX instructions may be encoded via the VEX prefix when the AVX-512
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/// instruction has a corresponding AVX/AVX2 opcode, when vector length
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/// accessed by instruction is less than 512 bits and when it does not use
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// the xmm or the mask registers or xmm/ymm registers with indexes higher than 15.
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/// The pass applies code reduction on the generated code for AVX-512 instrs.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "MCTargetDesc/X86InstComments.h"
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Pass.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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// Including the generated EVEX2VEX tables.
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struct X86EvexToVexCompressTableEntry {
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uint16_t EvexOpcode;
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uint16_t VexOpcode;
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bool operator<(const X86EvexToVexCompressTableEntry &RHS) const {
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return EvexOpcode < RHS.EvexOpcode;
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}
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friend bool operator<(const X86EvexToVexCompressTableEntry &TE,
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unsigned Opc) {
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return TE.EvexOpcode < Opc;
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}
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};
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#include "X86GenEVEX2VEXTables.inc"
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#define EVEX2VEX_DESC "Compressing EVEX instrs to VEX encoding when possible"
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#define EVEX2VEX_NAME "x86-evex-to-vex-compress"
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#define DEBUG_TYPE EVEX2VEX_NAME
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namespace {
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class EvexToVexInstPass : public MachineFunctionPass {
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/// For EVEX instructions that can be encoded using VEX encoding, replace
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/// them by the VEX encoding in order to reduce size.
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bool CompressEvexToVexImpl(MachineInstr &MI) const;
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public:
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static char ID;
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EvexToVexInstPass() : MachineFunctionPass(ID) { }
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StringRef getPassName() const override { return EVEX2VEX_DESC; }
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/// Loop over all of the basic blocks, replacing EVEX instructions
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/// by equivalent VEX instructions when possible for reducing code size.
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bool runOnMachineFunction(MachineFunction &MF) override;
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// This pass runs after regalloc and doesn't support VReg operands.
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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private:
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/// Machine instruction info used throughout the class.
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const X86InstrInfo *TII = nullptr;
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};
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} // end anonymous namespace
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char EvexToVexInstPass::ID = 0;
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bool EvexToVexInstPass::runOnMachineFunction(MachineFunction &MF) {
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TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
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const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
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if (!ST.hasAVX512())
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return false;
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bool Changed = false;
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/// Go over all basic blocks in function and replace
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/// EVEX encoded instrs by VEX encoding when possible.
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for (MachineBasicBlock &MBB : MF) {
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// Traverse the basic block.
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for (MachineInstr &MI : MBB)
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Changed |= CompressEvexToVexImpl(MI);
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}
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return Changed;
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}
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static bool usesExtendedRegister(const MachineInstr &MI) {
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auto isHiRegIdx = [](unsigned Reg) {
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// Check for XMM register with indexes between 16 - 31.
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if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
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return true;
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// Check for YMM register with indexes between 16 - 31.
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if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
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return true;
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return false;
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};
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// Check that operands are not ZMM regs or
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// XMM/YMM regs with hi indexes between 16 - 31.
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for (const MachineOperand &MO : MI.explicit_operands()) {
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if (!MO.isReg())
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continue;
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Register Reg = MO.getReg();
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assert(!(Reg >= X86::ZMM0 && Reg <= X86::ZMM31) &&
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"ZMM instructions should not be in the EVEX->VEX tables");
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if (isHiRegIdx(Reg))
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return true;
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}
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return false;
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}
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// Do any custom cleanup needed to finalize the conversion.
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static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) {
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(void)NewOpc;
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unsigned Opc = MI.getOpcode();
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switch (Opc) {
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case X86::VALIGNDZ128rri:
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case X86::VALIGNDZ128rmi:
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case X86::VALIGNQZ128rri:
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case X86::VALIGNQZ128rmi: {
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assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) &&
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"Unexpected new opcode!");
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unsigned Scale = (Opc == X86::VALIGNQZ128rri ||
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Opc == X86::VALIGNQZ128rmi) ? 8 : 4;
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MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
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Imm.setImm(Imm.getImm() * Scale);
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break;
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}
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case X86::VSHUFF32X4Z256rmi:
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case X86::VSHUFF32X4Z256rri:
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case X86::VSHUFF64X2Z256rmi:
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case X86::VSHUFF64X2Z256rri:
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case X86::VSHUFI32X4Z256rmi:
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case X86::VSHUFI32X4Z256rri:
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case X86::VSHUFI64X2Z256rmi:
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case X86::VSHUFI64X2Z256rri: {
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assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr ||
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NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) &&
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"Unexpected new opcode!");
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MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
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int64_t ImmVal = Imm.getImm();
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// Set bit 5, move bit 1 to bit 4, copy bit 0.
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Imm.setImm(0x20 | ((ImmVal & 2) << 3) | (ImmVal & 1));
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break;
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}
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case X86::VRNDSCALEPDZ128rri:
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case X86::VRNDSCALEPDZ128rmi:
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case X86::VRNDSCALEPSZ128rri:
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case X86::VRNDSCALEPSZ128rmi:
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case X86::VRNDSCALEPDZ256rri:
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case X86::VRNDSCALEPDZ256rmi:
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case X86::VRNDSCALEPSZ256rri:
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case X86::VRNDSCALEPSZ256rmi:
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case X86::VRNDSCALESDZr:
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case X86::VRNDSCALESDZm:
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case X86::VRNDSCALESSZr:
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case X86::VRNDSCALESSZm:
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case X86::VRNDSCALESDZr_Int:
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case X86::VRNDSCALESDZm_Int:
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case X86::VRNDSCALESSZr_Int:
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case X86::VRNDSCALESSZm_Int:
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const MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
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int64_t ImmVal = Imm.getImm();
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// Ensure that only bits 3:0 of the immediate are used.
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if ((ImmVal & 0xf) != ImmVal)
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return false;
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break;
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}
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return true;
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}
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// For EVEX instructions that can be encoded using VEX encoding
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// replace them by the VEX encoding in order to reduce size.
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bool EvexToVexInstPass::CompressEvexToVexImpl(MachineInstr &MI) const {
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// VEX format.
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// # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1
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// [Prefixes] [VEX] OPCODE ModR/M [SIB] [DISP] [IMM]
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//
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// EVEX format.
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// # of bytes: 4 1 1 1 4 / 1 1
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// [Prefixes] EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate]
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const MCInstrDesc &Desc = MI.getDesc();
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// Check for EVEX instructions only.
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if ((Desc.TSFlags & X86II::EncodingMask) != X86II::EVEX)
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return false;
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// Check for EVEX instructions with mask or broadcast as in these cases
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// the EVEX prefix is needed in order to carry this information
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// thus preventing the transformation to VEX encoding.
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if (Desc.TSFlags & (X86II::EVEX_K | X86II::EVEX_B))
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return false;
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// Check for EVEX instructions with L2 set. These instructions are 512-bits
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// and can't be converted to VEX.
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if (Desc.TSFlags & X86II::EVEX_L2)
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return false;
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#ifndef NDEBUG
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// Make sure the tables are sorted.
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static std::atomic<bool> TableChecked(false);
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if (!TableChecked.load(std::memory_order_relaxed)) {
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assert(std::is_sorted(std::begin(X86EvexToVex128CompressTable),
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std::end(X86EvexToVex128CompressTable)) &&
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"X86EvexToVex128CompressTable is not sorted!");
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assert(std::is_sorted(std::begin(X86EvexToVex256CompressTable),
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std::end(X86EvexToVex256CompressTable)) &&
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"X86EvexToVex256CompressTable is not sorted!");
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TableChecked.store(true, std::memory_order_relaxed);
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}
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#endif
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// Use the VEX.L bit to select the 128 or 256-bit table.
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ArrayRef<X86EvexToVexCompressTableEntry> Table =
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(Desc.TSFlags & X86II::VEX_L) ? makeArrayRef(X86EvexToVex256CompressTable)
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: makeArrayRef(X86EvexToVex128CompressTable);
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auto I = llvm::lower_bound(Table, MI.getOpcode());
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if (I == Table.end() || I->EvexOpcode != MI.getOpcode())
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return false;
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unsigned NewOpc = I->VexOpcode;
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if (usesExtendedRegister(MI))
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return false;
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if (!performCustomAdjustments(MI, NewOpc))
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return false;
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MI.setDesc(TII->get(NewOpc));
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MI.setAsmPrinterFlag(X86::AC_EVEX_2_VEX);
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return true;
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}
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INITIALIZE_PASS(EvexToVexInstPass, EVEX2VEX_NAME, EVEX2VEX_DESC, false, false)
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FunctionPass *llvm::createX86EvexToVexInsts() {
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return new EvexToVexInstPass();
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}
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