llvm-project/llvm/test/MC/Disassembler/X86
Craig Topper cade635c77 [X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions.
The behavior in 64-bit mode is different between Intel and AMD CPUs. Intel ignores the 0x66 prefix. AMD does not. objump doesn't ignore the 0x66 prefix. Since LLVM aims to match objdump behavior, we should do the same.

While I was trying to fix this I had change brtarget16/32 to use ENCODING_IW/ID instead of ENCODING_Iv to get the 0x66+REX.W case to act sort of sanely. It's still wrong, but that's a problem for another day.

The change in encoding exposed the fact that 16-bit mode disassembly of relative jumps was creating JMP_4 with a 2 byte immediate. It should have been JMP_2. From just printing you can't tell the difference, but if you dumped the encoding it wouldn't have matched what we started with.

While fixing that, it exposed that jo/jno opcodes were missing from the switch that this patch deleted and there were no test cases for them.

Fixes PR38537.

llvm-svn: 339622
2018-08-13 22:06:28 +00:00
..
amd3dnow.txt [X86][3DNow!] Add PFRCP reg-reg disassembler test case (PR21168) 2018-02-17 14:58:16 +00:00
avx-512.txt [X86] Properly disassemble gather/scatter instructions where xmm4/ymm4/zmm4 are used as the index. 2018-06-06 19:15:15 +00:00
fp-stack.txt [X86] Run dos2unix on two disassembler tests. 2017-10-02 21:46:58 +00:00
gather-novsib.txt [X86] Don't allow gather/scatter to disassembler if memory operand does not use a SIB byte. 2017-10-22 04:32:30 +00:00
hex-immediates.txt
intel-syntax-32.txt [X86] Remove 'opaque ptr' from the intel syntax parser and printer. 2018-05-01 04:42:00 +00:00
intel-syntax.txt [X86] Remove 'opaque ptr' from the intel syntax parser and printer. 2018-05-01 04:42:00 +00:00
invalid-EVEX-R2.txt [X86][Disassembler] Make it an error to set EVEX.R' to 0 when modrm.reg encodes a GPR. 2018-06-01 06:11:29 +00:00
invalid-VEX-vvvv-32.txt [X86] Make sure the check for VEX.vvvv being all ones on instructions that don't use it doesn't ignore a bit in 32-bit mode. 2018-06-01 01:23:52 +00:00
invalid-VEX-vvvv.txt
lit.local.cfg
marked-up.txt
missing-sib.txt
moffs.txt
padlock.txt
prefixes-i386.txt Fix for Bug 34475 - LOCK/REP/REPNE prefixes emitted as instruction on their own. 2017-11-03 15:25:13 +00:00
prefixes-x86_64.txt Fix for Bug 34475 - LOCK/REP/REPNE prefixes emitted as instruction on their own. 2017-11-03 15:25:13 +00:00
prefixes.txt [X86][Disassembler] Fix LOCK prefix disassembler support 2018-07-05 23:32:42 +00:00
simple-tests.txt [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. 2018-01-12 06:21:36 +00:00
truncated-input.txt
x86-16.txt [X86] movdiri and movdir64b instructions 2018-05-01 10:01:16 +00:00
x86-32.txt [X86] Teach the disassembler to use %eiz/%riz instead of NoRegister when the SIB byte is present, but doesn't encode an index register and there was another shorter encoding that would achieve the same result. 2018-06-27 19:03:36 +00:00
x86-64-err.txt [X86] Teach the disassembler that some instructions use VEX.W==0 without a corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored. 2017-10-22 06:18:26 +00:00
x86-64.txt [X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions. 2018-08-13 22:06:28 +00:00