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llvm-project/llvm/test/Transforms/SLPVectorizer/AMDGPU
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Farhana Aleen 3b416db19b [SLP] Recognize min/max pattern using instructions producing same values. 
Summary: It is common to have the following min/max pattern during the intermediate stages of SLP since we only optimize at the end. This patch tries to catch such patterns and allow more vectorization.

         %1 = extractelement <2 x i32> %a, i32 0
         %2 = extractelement <2 x i32> %a, i32 1
         %cond = icmp sgt i32 %1, %2
         %3 = extractelement <2 x i32> %a, i32 0
         %4 = extractelement <2 x i32> %a, i32 1
         %select = select i1 %cond, i32 %3, i32 %4

Author: FarhanaAleen

Reviewed By: ABataev, RKSimon, spatel

Differential Revision: https://reviews.llvm.org/D47608

llvm-svn: 336130
 		2018-07-02 17:55:31 +00:00
..
horizontal-store.ll [SLP] Recognize min/max pattern using instructions producing same values. 2018-07-02 17:55:31 +00:00
lit.local.cfg
…
packed-math.ll AMDGPU: Make v2i16/v2f16 legal on VI 2018-05-22 06:32:10 +00:00
reduction.ll [AMDGPU] Support horizontal vectorization of min/max. 2018-05-09 21:18:34 +00:00