Amara Emerson e3f5046e44 [AArch64][GlobalISel] Merge selection of vector-vector G_ASHR/G_LSHR and support more cases. ... The vector-immediate cases are handled elsewhere in an earlier commit.		2020-09-21 16:04:52 -07:00
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AArch64CallLowering.cpp	AArch64: Use Register	2020-07-22 14:14:44 -04:00
AArch64CallLowering.h	[SVE][CodeGen] Fix bug when falling back to DAG ISel	2020-07-07 09:23:04 +01:00
AArch64InstructionSelector.cpp	[AArch64][GlobalISel] Merge selection of vector-vector G_ASHR/G_LSHR and support more cases.	2020-09-21 16:04:52 -07:00
AArch64LegalizerInfo.cpp	[AArch64][GlobalISel] Make <4 x s16> G_ASHR and G_LSHR legal.	2020-09-21 15:32:48 -07:00
AArch64LegalizerInfo.h	GlobalISel: Pass LegalizerHelper to custom legalize callbacks	2020-06-18 17:17:38 -04:00
AArch64PostLegalizerCombiner.cpp	[AArch64][GlobalISel] Add a post-legalize combine for lowering vector-immediate G_ASHR/G_LSHR.	2020-09-21 16:04:52 -07:00
AArch64PreLegalizerCombiner.cpp	GlobalISel: Add generic instructions for memory intrinsics	2020-08-26 20:08:45 -04:00
AArch64RegisterBankInfo.cpp	[AArch64][GlobalISel] Handle rtcGPR64RegClassID in AArch64RegisterBankInfo::getRegBankFromRegClass()	2020-08-19 12:52:30 -07:00
AArch64RegisterBankInfo.h	[AArch64] Move RegisterBankInfo.cpp/h to GISel.	2020-06-09 23:26:25 -07:00