forked from OSchip/llvm-project
344 lines
12 KiB
Plaintext
344 lines
12 KiB
Plaintext
//===- README_ALTIVEC.txt - Notes for improving Altivec code gen ----------===//
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Implement PPCInstrInfo::isLoadFromStackSlot/isStoreToStackSlot for vector
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registers, to generate better spill code.
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//===----------------------------------------------------------------------===//
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The first should be a single lvx from the constant pool, the second should be
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a xor/stvx:
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void foo(void) {
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int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 17, 1, 1, 1, 1 };
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bar (x);
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}
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#include <string.h>
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void foo(void) {
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int x[8] __attribute__((aligned(128)));
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memset (x, 0, sizeof (x));
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bar (x);
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}
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//===----------------------------------------------------------------------===//
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Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=8763
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When -ffast-math is on, we can use 0.0.
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//===----------------------------------------------------------------------===//
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Consider this:
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v4f32 Vector;
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v4f32 Vector2 = { Vector.X, Vector.X, Vector.X, Vector.X };
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Since we know that "Vector" is 16-byte aligned and we know the element offset
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of ".X", we should change the load into a lve*x instruction, instead of doing
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a load/store/lve*x sequence.
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//===----------------------------------------------------------------------===//
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For functions that use altivec AND have calls, we are VRSAVE'ing all call
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clobbered regs.
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//===----------------------------------------------------------------------===//
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Implement passing vectors by value into calls and receiving them as arguments.
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//===----------------------------------------------------------------------===//
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GCC apparently tries to codegen { C1, C2, Variable, C3 } as a constant pool load
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of C1/C2/C3, then a load and vperm of Variable.
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//===----------------------------------------------------------------------===//
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We need a way to teach tblgen that some operands of an intrinsic are required to
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be constants. The verifier should enforce this constraint.
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//===----------------------------------------------------------------------===//
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We currently codegen SCALAR_TO_VECTOR as a store of the scalar to a 16-byte
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aligned stack slot, followed by a load/vperm. We should probably just store it
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to a scalar stack slot, then use lvsl/vperm to load it. If the value is already
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in memory this is a big win.
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//===----------------------------------------------------------------------===//
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extract_vector_elt of an arbitrary constant vector can be done with the
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following instructions:
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vTemp = vec_splat(v0,2); // 2 is the element the src is in.
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vec_ste(&destloc,0,vTemp);
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We can do an arbitrary non-constant value by using lvsr/perm/ste.
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//===----------------------------------------------------------------------===//
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If we want to tie instruction selection into the scheduler, we can do some
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constant formation with different instructions. For example, we can generate
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"vsplti -1" with "vcmpequw R,R" and 1,1,1,1 with "vsubcuw R,R", and 0,0,0,0 with
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"vsplti 0" or "vxor", each of which use different execution units, thus could
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help scheduling.
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This is probably only reasonable for a post-pass scheduler.
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//===----------------------------------------------------------------------===//
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For this function:
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void test(vector float *A, vector float *B) {
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vector float C = (vector float)vec_cmpeq(*A, *B);
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if (!vec_any_eq(*A, *B))
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*B = (vector float){0,0,0,0};
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*A = C;
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}
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we get the following basic block:
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...
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lvx v2, 0, r4
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lvx v3, 0, r3
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vcmpeqfp v4, v3, v2
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vcmpeqfp. v2, v3, v2
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bne cr6, LBB1_2 ; cond_next
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The vcmpeqfp/vcmpeqfp. instructions currently cannot be merged when the
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vcmpeqfp. result is used by a branch. This can be improved.
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//===----------------------------------------------------------------------===//
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The code generated for this is truly aweful:
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vector float test(float a, float b) {
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return (vector float){ 0.0, a, 0.0, 0.0};
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}
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LCPI1_0: ; float
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.space 4
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.text
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.globl _test
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.align 4
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_test:
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mfspr r2, 256
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oris r3, r2, 4096
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mtspr 256, r3
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lis r3, ha16(LCPI1_0)
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addi r4, r1, -32
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stfs f1, -16(r1)
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addi r5, r1, -16
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lfs f0, lo16(LCPI1_0)(r3)
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stfs f0, -32(r1)
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lvx v2, 0, r4
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lvx v3, 0, r5
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vmrghw v3, v3, v2
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vspltw v2, v2, 0
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vmrghw v2, v2, v3
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mtspr 256, r2
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blr
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//===----------------------------------------------------------------------===//
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int foo(vector float *x, vector float *y) {
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if (vec_all_eq(*x,*y)) return 3245;
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else return 12;
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}
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A predicate compare being used in a select_cc should have the same peephole
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applied to it as a predicate compare used by a br_cc. There should be no
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mfcr here:
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_foo:
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mfspr r2, 256
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oris r5, r2, 12288
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mtspr 256, r5
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li r5, 12
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li r6, 3245
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lvx v2, 0, r4
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lvx v3, 0, r3
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vcmpeqfp. v2, v3, v2
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mfcr r3, 2
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rlwinm r3, r3, 25, 31, 31
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cmpwi cr0, r3, 0
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bne cr0, LBB1_2 ; entry
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LBB1_1: ; entry
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mr r6, r5
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LBB1_2: ; entry
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mr r3, r6
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mtspr 256, r2
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blr
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//===----------------------------------------------------------------------===//
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CodeGen/PowerPC/vec_constants.ll has an and operation that should be
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codegen'd to andc. The issue is that the 'all ones' build vector is
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SelectNodeTo'd a VSPLTISB instruction node before the and/xor is selected
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which prevents the vnot pattern from matching.
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//===----------------------------------------------------------------------===//
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An alternative to the store/store/load approach for illegal insert element
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lowering would be:
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1. store element to any ol' slot
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2. lvx the slot
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3. lvsl 0; splat index; vcmpeq to generate a select mask
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4. lvsl slot + x; vperm to rotate result into correct slot
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5. vsel result together.
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//===----------------------------------------------------------------------===//
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Should codegen branches on vec_any/vec_all to avoid mfcr. Two examples:
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#include <altivec.h>
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int f(vector float a, vector float b)
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{
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int aa = 0;
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if (vec_all_ge(a, b))
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aa |= 0x1;
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if (vec_any_ge(a,b))
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aa |= 0x2;
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return aa;
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}
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vector float f(vector float a, vector float b) {
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if (vec_any_eq(a, b))
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return a;
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else
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return b;
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}
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//===----------------------------------------------------------------------===//
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We should do a little better with eliminating dead stores.
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The stores to the stack are dead since %a and %b are not needed
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; Function Attrs: nounwind
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define <16 x i8> @test_vpmsumb() #0 {
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entry:
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%a = alloca <16 x i8>, align 16
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%b = alloca <16 x i8>, align 16
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store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %a, align 16
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store <16 x i8> <i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 112>, <16 x i8>* %b, align 16
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%0 = load <16 x i8>* %a, align 16
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%1 = load <16 x i8>* %b, align 16
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%2 = call <16 x i8> @llvm.ppc.altivec.crypto.vpmsumb(<16 x i8> %0, <16 x i8> %1)
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ret <16 x i8> %2
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}
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; Function Attrs: nounwind readnone
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declare <16 x i8> @llvm.ppc.altivec.crypto.vpmsumb(<16 x i8>, <16 x i8>) #1
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Produces the following code with -mtriple=powerpc64-unknown-linux-gnu:
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# %bb.0: # %entry
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addis 3, 2, .LCPI0_0@toc@ha
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addis 4, 2, .LCPI0_1@toc@ha
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addi 3, 3, .LCPI0_0@toc@l
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addi 4, 4, .LCPI0_1@toc@l
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lxvw4x 0, 0, 3
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addi 3, 1, -16
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lxvw4x 35, 0, 4
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stxvw4x 0, 0, 3
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ori 2, 2, 0
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lxvw4x 34, 0, 3
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addi 3, 1, -32
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stxvw4x 35, 0, 3
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vpmsumb 2, 2, 3
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blr
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.long 0
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.quad 0
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The two stxvw4x instructions are not needed.
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With -mtriple=powerpc64le-unknown-linux-gnu, the associated permutes
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are present too.
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//===----------------------------------------------------------------------===//
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The following example is found in test/CodeGen/PowerPC/vec_add_sub_doubleword.ll:
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define <2 x i64> @increment_by_val(<2 x i64> %x, i64 %val) nounwind {
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%tmpvec = insertelement <2 x i64> <i64 0, i64 0>, i64 %val, i32 0
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%tmpvec2 = insertelement <2 x i64> %tmpvec, i64 %val, i32 1
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%result = add <2 x i64> %x, %tmpvec2
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ret <2 x i64> %result
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This will generate the following instruction sequence:
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std 5, -8(1)
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std 5, -16(1)
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addi 3, 1, -16
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ori 2, 2, 0
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lxvd2x 35, 0, 3
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vaddudm 2, 2, 3
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blr
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This will almost certainly cause a load-hit-store hazard.
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Since val is a value parameter, it should not need to be saved onto
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the stack, unless it's being done set up the vector register. Instead,
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it would be better to splat the value into a vector register, and then
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remove the (dead) stores to the stack.
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//===----------------------------------------------------------------------===//
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At the moment we always generate a lxsdx in preference to lfd, or stxsdx in
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preference to stfd. When we have a reg-immediate addressing mode, this is a
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poor choice, since we have to load the address into an index register. This
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should be fixed for P7/P8.
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//===----------------------------------------------------------------------===//
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Right now, ShuffleKind 0 is supported only on BE, and ShuffleKind 2 only on LE.
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However, we could actually support both kinds on either endianness, if we check
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for the appropriate shufflevector pattern for each case ... this would cause
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some additional shufflevectors to be recognized and implemented via the
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"swapped" form.
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//===----------------------------------------------------------------------===//
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There is a utility program called PerfectShuffle that generates a table of the
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shortest instruction sequence for implementing a shufflevector operation on
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PowerPC. However, this was designed for big-endian code generation. We could
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modify this program to create a little endian version of the table. The table
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is used in PPCISelLowering.cpp, PPCTargetLowering::LOWERVECTOR_SHUFFLE().
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//===----------------------------------------------------------------------===//
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Opportunies to use instructions from PPCInstrVSX.td during code gen
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- Conversion instructions (Sections 7.6.1.5 and 7.6.1.6 of ISA 2.07)
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- Scalar comparisons (xscmpodp and xscmpudp)
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- Min and max (xsmaxdp, xsmindp, xvmaxdp, xvmindp, xvmaxsp, xvminsp)
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Related to this: we currently do not generate the lxvw4x instruction for either
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v4f32 or v4i32, probably because adding a dag pattern to the recognizer requires
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a single target type. This should probably be addressed in the PPCISelDAGToDAG logic.
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//===----------------------------------------------------------------------===//
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Currently EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT are type-legal only
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for v2f64 with VSX available. We should create custom lowering
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support for the other vector types. Without this support, we generate
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sequences with load-hit-store hazards.
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v4f32 can be supported with VSX by shifting the correct element into
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big-endian lane 0, using xscvspdpn to produce a double-precision
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representation of the single-precision value in big-endian
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double-precision lane 0, and reinterpreting lane 0 as an FPR or
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vector-scalar register.
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v2i64 can be supported with VSX and P8Vector in the same manner as
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v2f64, followed by a direct move to a GPR.
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v4i32 can be supported with VSX and P8Vector by shifting the correct
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element into big-endian lane 1, using a direct move to a GPR, and
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sign-extending the 32-bit result to 64 bits.
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v8i16 can be supported with VSX and P8Vector by shifting the correct
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element into big-endian lane 3, using a direct move to a GPR, and
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sign-extending the 16-bit result to 64 bits.
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v16i8 can be supported with VSX and P8Vector by shifting the correct
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element into big-endian lane 7, using a direct move to a GPR, and
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sign-extending the 8-bit result to 64 bits.
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