forked from OSchip/llvm-project
139 lines
4.1 KiB
LLVM
139 lines
4.1 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
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@A = common global fp128 0xL00000000000000000000000000000000, align 16
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@B = common global fp128 0xL00000000000000000000000000000000, align 16
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@C = common global fp128 0xL00000000000000000000000000000000, align 16
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@D = common global fp128 0xL00000000000000000000000000000000, align 16
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define fp128 @testSqrtOdd(fp128 %a) {
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entry:
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%0 = call fp128 @llvm.ppc.sqrtf128.round.to.odd(fp128 %a)
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ret fp128 %0
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; CHECK-LABEL: testSqrtOdd
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; CHECK: xssqrtqpo v2, v2
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; CHECK: blr
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}
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declare fp128 @llvm.ppc.sqrtf128.round.to.odd(fp128)
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define void @testFMAOdd(fp128 %a, fp128 %b, fp128 %c) {
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entry:
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%0 = call fp128 @llvm.ppc.fmaf128.round.to.odd(fp128 %a, fp128 %b, fp128 %c)
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store fp128 %0, fp128* @A, align 16
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%sub = fsub fp128 0xL00000000000000008000000000000000, %c
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%1 = call fp128 @llvm.ppc.fmaf128.round.to.odd(fp128 %a, fp128 %b, fp128 %sub)
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store fp128 %1, fp128* @B, align 16
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%2 = call fp128 @llvm.ppc.fmaf128.round.to.odd(fp128 %a, fp128 %b, fp128 %c)
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%sub1 = fsub fp128 0xL00000000000000008000000000000000, %2
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store fp128 %sub1, fp128* @C, align 16
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%sub2 = fsub fp128 0xL00000000000000008000000000000000, %c
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%3 = call fp128 @llvm.ppc.fmaf128.round.to.odd(fp128 %a, fp128 %b, fp128 %sub2)
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%sub3 = fsub fp128 0xL00000000000000008000000000000000, %3
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store fp128 %sub3, fp128* @D, align 16
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ret void
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; CHECK-LABEL: testFMAOdd
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; CHECK-DAG: xsmaddqpo v{{[0-9]+}}, v2, v3
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; CHECK-DAG: xsmsubqpo v{{[0-9]+}}, v2, v3
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; CHECK-DAG: xsnmaddqpo v{{[0-9]+}}, v2, v3
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; CHECK-DAG: xsnmsubqpo v{{[0-9]+}}, v2, v3
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; CHECK: blr
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}
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declare fp128 @llvm.ppc.fmaf128.round.to.odd(fp128, fp128, fp128)
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define fp128 @testAddOdd(fp128 %a, fp128 %b) {
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entry:
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%0 = call fp128 @llvm.ppc.addf128.round.to.odd(fp128 %a, fp128 %b)
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ret fp128 %0
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; CHECK-LABEL: testAddOdd
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; CHECK: xsaddqpo v2, v2, v3
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; CHECK: blr
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}
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declare fp128 @llvm.ppc.addf128.round.to.odd(fp128, fp128)
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define fp128 @testSubOdd(fp128 %a, fp128 %b) {
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entry:
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%0 = call fp128 @llvm.ppc.subf128.round.to.odd(fp128 %a, fp128 %b)
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ret fp128 %0
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; CHECK-LABEL: testSubOdd
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; CHECK: xssubqpo v2, v2, v3
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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declare fp128 @llvm.ppc.subf128.round.to.odd(fp128, fp128)
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; Function Attrs: noinline nounwind optnone
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define fp128 @testMulOdd(fp128 %a, fp128 %b) {
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entry:
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%0 = call fp128 @llvm.ppc.mulf128.round.to.odd(fp128 %a, fp128 %b)
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ret fp128 %0
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; CHECK-LABEL: testMulOdd
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; CHECK: xsmulqpo v2, v2, v3
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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declare fp128 @llvm.ppc.mulf128.round.to.odd(fp128, fp128)
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define fp128 @testDivOdd(fp128 %a, fp128 %b) {
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entry:
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%0 = call fp128 @llvm.ppc.divf128.round.to.odd(fp128 %a, fp128 %b)
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ret fp128 %0
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; CHECK-LABEL: testDivOdd
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; CHECK: xsdivqpo v2, v2, v3
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; CHECK: blr
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}
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declare fp128 @llvm.ppc.divf128.round.to.odd(fp128, fp128)
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define double @testTruncOdd(fp128 %a) {
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entry:
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%0 = call double @llvm.ppc.truncf128.round.to.odd(fp128 %a)
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ret double %0
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; CHECK-LABEL: testTruncOdd
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; CHECK: xscvqpdpo v2, v2
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; CHECK: xscpsgndp f1, v2, v2
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; CHECK: blr
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}
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declare double @llvm.ppc.truncf128.round.to.odd(fp128)
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; Function Attrs: noinline nounwind optnone
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define fp128 @insert_exp_qp(i64 %b) {
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entry:
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%b.addr = alloca i64, align 8
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store i64 %b, i64* %b.addr, align 8
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%0 = load fp128, fp128* @A, align 16
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%1 = load i64, i64* %b.addr, align 8
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%2 = call fp128 @llvm.ppc.scalar.insert.exp.qp(fp128 %0, i64 %1)
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ret fp128 %2
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; CHECK-LABEL: insert_exp_qp
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; CHECK-DAG: mtfprd [[FPREG:f[0-9]+]], r3
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; CHECK-DAG: lxvx [[VECREG:v[0-9]+]]
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; CHECK: xsiexpqp v2, [[VECREG]], [[FPREG]]
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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declare fp128 @llvm.ppc.scalar.insert.exp.qp(fp128, i64)
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; Function Attrs: noinline nounwind optnone
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define i64 @extract_exp() {
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entry:
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%0 = load fp128, fp128* @A, align 16
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%1 = call i64 @llvm.ppc.scalar.extract.expq(fp128 %0)
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ret i64 %1
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; CHECK-LABEL: extract_exp
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; CHECK: lxvx [[VECIN:v[0-9]+]]
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; CHECK: xsxexpqp [[VECOUT:v[0-9]+]], [[VECIN]]
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; CHECK: mfvsrd r3, [[VECOUT]]
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.ppc.scalar.extract.expq(fp128)
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