forked from OSchip/llvm-project
168 lines
6.1 KiB
LLVM
168 lines
6.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
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; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
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define arm_aapcs_vfpcc void @vabd_v4f32(<4 x float> %x, <4 x float> %y, <4 x float>* %z) {
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; CHECK-MVE-LABEL: vabd_v4f32:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: .save {r4, r5, r6, r7, lr}
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; CHECK-MVE-NEXT: push {r4, r5, r6, r7, lr}
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; CHECK-MVE-NEXT: .pad #4
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; CHECK-MVE-NEXT: sub sp, #4
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; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
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; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
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; CHECK-MVE-NEXT: vmov q4, q1
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; CHECK-MVE-NEXT: vmov q5, q0
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; CHECK-MVE-NEXT: mov r4, r0
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; CHECK-MVE-NEXT: vmov r0, s20
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; CHECK-MVE-NEXT: vmov r1, s16
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; CHECK-MVE-NEXT: bl __aeabi_fsub
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; CHECK-MVE-NEXT: mov r5, r0
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; CHECK-MVE-NEXT: vmov r0, s21
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; CHECK-MVE-NEXT: vmov r1, s17
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; CHECK-MVE-NEXT: bl __aeabi_fsub
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; CHECK-MVE-NEXT: mov r6, r0
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; CHECK-MVE-NEXT: vmov r0, s22
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; CHECK-MVE-NEXT: vmov r1, s18
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; CHECK-MVE-NEXT: bl __aeabi_fsub
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; CHECK-MVE-NEXT: mov r7, r0
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; CHECK-MVE-NEXT: vmov r0, s23
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; CHECK-MVE-NEXT: vmov r1, s19
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; CHECK-MVE-NEXT: bl __aeabi_fsub
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; CHECK-MVE-NEXT: bic r0, r0, #-2147483648
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; CHECK-MVE-NEXT: vmov s3, r0
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; CHECK-MVE-NEXT: bic r0, r7, #-2147483648
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; CHECK-MVE-NEXT: vmov s2, r0
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; CHECK-MVE-NEXT: bic r0, r6, #-2147483648
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; CHECK-MVE-NEXT: vmov s1, r0
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; CHECK-MVE-NEXT: bic r0, r5, #-2147483648
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; CHECK-MVE-NEXT: vmov s0, r0
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; CHECK-MVE-NEXT: vstrw.32 q0, [r4]
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; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
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; CHECK-MVE-NEXT: add sp, #4
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; CHECK-MVE-NEXT: pop {r4, r5, r6, r7, pc}
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;
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; CHECK-MVEFP-LABEL: vabd_v4f32:
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; CHECK-MVEFP: @ %bb.0: @ %entry
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; CHECK-MVEFP-NEXT: vabd.f32 q0, q0, q1
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; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
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; CHECK-MVEFP-NEXT: bx lr
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entry:
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%0 = fsub <4 x float> %x, %y
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%1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %z, align 4
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ret void
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}
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define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, <8 x half>* %z) {
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; CHECK-MVE-LABEL: vabd_v8f16:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: .save {r4, r5, r6, lr}
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; CHECK-MVE-NEXT: push {r4, r5, r6, lr}
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; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
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; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11, d12, d13}
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; CHECK-MVE-NEXT: mov r4, r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q1[1]
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; CHECK-MVE-NEXT: vmov q5, q1
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; CHECK-MVE-NEXT: vmov q4, q0
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r5, r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q4[1]
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r1, r5
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; CHECK-MVE-NEXT: bl __aeabi_fsub
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; CHECK-MVE-NEXT: mov r5, r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q5[0]
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r6, r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q4[0]
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r1, r6
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; CHECK-MVE-NEXT: bl __aeabi_fsub
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; CHECK-MVE-NEXT: bic r0, r0, #-2147483648
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; CHECK-MVE-NEXT: bl __aeabi_f2h
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; CHECK-MVE-NEXT: vmov.16 q6[0], r0
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; CHECK-MVE-NEXT: bic r0, r5, #-2147483648
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; CHECK-MVE-NEXT: bl __aeabi_f2h
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; CHECK-MVE-NEXT: vmov.16 q6[1], r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q5[2]
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r5, r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q4[2]
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r1, r5
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; CHECK-MVE-NEXT: bl __aeabi_fsub
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; CHECK-MVE-NEXT: bic r0, r0, #-2147483648
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; CHECK-MVE-NEXT: bl __aeabi_f2h
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; CHECK-MVE-NEXT: vmov.16 q6[2], r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q5[3]
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r5, r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q4[3]
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r1, r5
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; CHECK-MVE-NEXT: bl __aeabi_fsub
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; CHECK-MVE-NEXT: bic r0, r0, #-2147483648
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; CHECK-MVE-NEXT: bl __aeabi_f2h
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; CHECK-MVE-NEXT: vmov.16 q6[3], r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q5[4]
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r5, r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q4[4]
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r1, r5
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; CHECK-MVE-NEXT: bl __aeabi_fsub
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; CHECK-MVE-NEXT: bic r0, r0, #-2147483648
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; CHECK-MVE-NEXT: bl __aeabi_f2h
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; CHECK-MVE-NEXT: vmov.16 q6[4], r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q5[5]
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r5, r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q4[5]
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r1, r5
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; CHECK-MVE-NEXT: bl __aeabi_fsub
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; CHECK-MVE-NEXT: bic r0, r0, #-2147483648
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; CHECK-MVE-NEXT: bl __aeabi_f2h
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; CHECK-MVE-NEXT: vmov.16 q6[5], r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q5[6]
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r5, r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q4[6]
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r1, r5
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; CHECK-MVE-NEXT: bl __aeabi_fsub
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; CHECK-MVE-NEXT: bic r0, r0, #-2147483648
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; CHECK-MVE-NEXT: bl __aeabi_f2h
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; CHECK-MVE-NEXT: vmov.16 q6[6], r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q5[7]
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r5, r0
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; CHECK-MVE-NEXT: vmov.u16 r0, q4[7]
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; CHECK-MVE-NEXT: bl __aeabi_h2f
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; CHECK-MVE-NEXT: mov r1, r5
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; CHECK-MVE-NEXT: bl __aeabi_fsub
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; CHECK-MVE-NEXT: bic r0, r0, #-2147483648
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; CHECK-MVE-NEXT: bl __aeabi_f2h
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; CHECK-MVE-NEXT: vmov.16 q6[7], r0
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; CHECK-MVE-NEXT: vstrw.32 q6, [r4]
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; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11, d12, d13}
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; CHECK-MVE-NEXT: pop {r4, r5, r6, pc}
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;
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; CHECK-MVEFP-LABEL: vabd_v8f16:
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; CHECK-MVEFP: @ %bb.0: @ %entry
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; CHECK-MVEFP-NEXT: vabd.f16 q0, q0, q1
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; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
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; CHECK-MVEFP-NEXT: bx lr
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entry:
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%0 = fsub <8 x half> %x, %y
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%1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
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store <8 x half> %1, <8 x half>* %z
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ret void
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}
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declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
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declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
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