forked from OSchip/llvm-project
35 lines
1.1 KiB
C
35 lines
1.1 KiB
C
// REQUIRES: arm-registered-target
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// RUN: %clang_cc1 -triple thumbv7-apple-darwin \
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// RUN: -target-abi apcs-gnu \
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// RUN: -target-cpu cortex-a8 \
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// RUN: -mfloat-abi soft \
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// RUN: -target-feature +soft-float-abi \
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// RUN: -ffreestanding \
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// RUN: -emit-llvm -w -o - %s | FileCheck %s
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#include <arm_neon.h>
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// Radar 11998303: Avoid using i64 types for vld1q_lane and vst1q_lane Neon
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// intrinsics with <2 x i64> vectors to avoid poor code for i64 in the backend.
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void t1(uint64_t *src, uint8_t *dst) {
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// CHECK: @t1
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uint64x2_t q = vld1q_u64(src);
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// CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64
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vst1q_lane_u64(dst, q, 1);
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// CHECK: bitcast <16 x i8> %{{.*}} to <2 x i64>
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// CHECK: shufflevector <2 x i64>
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// CHECK: call void @llvm.arm.neon.vst1.v1i64
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}
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void t2(uint64_t *src1, uint8_t *src2, uint64x2_t *dst) {
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// CHECK: @t2
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uint64x2_t q = vld1q_u64(src1);
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// CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64
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q = vld1q_lane_u64(src2, q, 0);
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// CHECK: shufflevector <2 x i64>
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// CHECK: call <1 x i64> @llvm.arm.neon.vld1.v1i64
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// CHECK: shufflevector <1 x i64>
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*dst = q;
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// CHECK: store <2 x i64>
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}
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