forked from OSchip/llvm-project
37 lines
1.3 KiB
LLVM
37 lines
1.3 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; This test is for a bug in
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; DAGCombiner::reduceBuildVecConvertToConvertBuildVec() where
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; the wrong type was being passed to
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; TargetLowering::getOperationAction() when checking the legality of
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; ISD::UINT_TO_FP and ISD::SINT_TO_FP opcodes.
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; CHECK: @sint
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; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @sint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
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entry:
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%ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%sint = load i32 addrspace(1) * %in
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%conv = sitofp i32 %sint to float
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%0 = insertelement <4 x float> undef, float %conv, i32 0
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%splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
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store <4 x float> %splat, <4 x float> addrspace(1)* %out
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ret void
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}
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;CHECK: @uint
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;CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @uint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
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entry:
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%ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%uint = load i32 addrspace(1) * %in
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%conv = uitofp i32 %uint to float
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%0 = insertelement <4 x float> undef, float %conv, i32 0
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%splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
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store <4 x float> %splat, <4 x float> addrspace(1)* %out
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ret void
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}
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