forked from OSchip/llvm-project
81 lines
2.0 KiB
LLVM
81 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s
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; Verify that for the architectures that are known to have poor latency
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; double precision shift instructions we generate alternative sequence
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; of instructions with lower latencies instead of shld instruction.
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;uint64_t lshift1(uint64_t a, uint64_t b)
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;{
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; return (a << 1) | (b >> 63);
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;}
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define i64 @lshift1(i64 %a, i64 %b) nounwind readnone uwtable {
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; CHECK-LABEL: lshift1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: shrq $63, %rsi
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; CHECK-NEXT: leaq (%rsi,%rdi,2), %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, 1
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%shr = lshr i64 %b, 63
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%or = or i64 %shr, %shl
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ret i64 %or
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}
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;uint64_t lshift2(uint64_t a, uint64_t b)
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;{
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; return (a << 2) | (b >> 62);
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;}
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define i64 @lshift2(i64 %a, i64 %b) nounwind readnone uwtable {
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; CHECK-LABEL: lshift2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: shrq $62, %rsi
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; CHECK-NEXT: leaq (%rsi,%rdi,4), %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, 2
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%shr = lshr i64 %b, 62
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%or = or i64 %shr, %shl
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ret i64 %or
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}
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;uint64_t lshift7(uint64_t a, uint64_t b)
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;{
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; return (a << 7) | (b >> 57);
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;}
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define i64 @lshift7(i64 %a, i64 %b) nounwind readnone uwtable {
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; CHECK-LABEL: lshift7:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: shrq $57, %rsi
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; CHECK-NEXT: shlq $7, %rdi
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; CHECK-NEXT: leaq (%rdi,%rsi), %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, 7
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%shr = lshr i64 %b, 57
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%or = or i64 %shr, %shl
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ret i64 %or
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}
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;uint64_t lshift63(uint64_t a, uint64_t b)
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;{
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; return (a << 63) | (b >> 1);
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;}
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define i64 @lshift63(i64 %a, i64 %b) nounwind readnone uwtable {
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; CHECK-LABEL: lshift63:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: shrq %rsi
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; CHECK-NEXT: shlq $63, %rdi
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; CHECK-NEXT: leaq (%rdi,%rsi), %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, 63
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%shr = lshr i64 %b, 1
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%or = or i64 %shr, %shl
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ret i64 %or
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}
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