forked from OSchip/llvm-project
136 lines
3.6 KiB
LLVM
136 lines
3.6 KiB
LLVM
; RUN: opt -O3 -S < %s | FileCheck %s
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; Show 'optnone' suppresses optimizations.
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; Two attribute groups that differ only by 'optnone'.
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; 'optnone' requires 'noinline' so #0 is 'noinline' by itself,
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; even though it would otherwise be irrelevant to this example.
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attributes #0 = { noinline }
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attributes #1 = { noinline optnone }
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; int iadd(int a, int b){ return a + b; }
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define i32 @iadd_optimize(i32 %a, i32 %b) #0 {
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entry:
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%a.addr = alloca i32, align 4
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%b.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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store i32 %b, i32* %b.addr, align 4
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%0 = load i32, i32* %a.addr, align 4
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%1 = load i32, i32* %b.addr, align 4
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%add = add nsw i32 %0, %1
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ret i32 %add
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}
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; CHECK-LABEL: @iadd_optimize
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; CHECK-NOT: alloca
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; CHECK-NOT: store
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; CHECK-NOT: load
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; CHECK: ret
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define i32 @iadd_optnone(i32 %a, i32 %b) #1 {
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entry:
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%a.addr = alloca i32, align 4
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%b.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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store i32 %b, i32* %b.addr, align 4
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%0 = load i32, i32* %a.addr, align 4
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%1 = load i32, i32* %b.addr, align 4
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%add = add nsw i32 %0, %1
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ret i32 %add
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}
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; CHECK-LABEL: @iadd_optnone
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; CHECK: alloca i32
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; CHECK: alloca i32
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; CHECK: store i32
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; CHECK: store i32
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; CHECK: load i32
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; CHECK: load i32
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; CHECK: add nsw i32
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; CHECK: ret i32
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; float fsub(float a, float b){ return a - b; }
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define float @fsub_optimize(float %a, float %b) #0 {
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entry:
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%a.addr = alloca float, align 4
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%b.addr = alloca float, align 4
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store float %a, float* %a.addr, align 4
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store float %b, float* %b.addr, align 4
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%0 = load float, float* %a.addr, align 4
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%1 = load float, float* %b.addr, align 4
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%sub = fsub float %0, %1
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ret float %sub
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}
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; CHECK-LABEL: @fsub_optimize
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; CHECK-NOT: alloca
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; CHECK-NOT: store
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; CHECK-NOT: load
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; CHECK: ret
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define float @fsub_optnone(float %a, float %b) #1 {
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entry:
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%a.addr = alloca float, align 4
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%b.addr = alloca float, align 4
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store float %a, float* %a.addr, align 4
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store float %b, float* %b.addr, align 4
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%0 = load float, float* %a.addr, align 4
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%1 = load float, float* %b.addr, align 4
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%sub = fsub float %0, %1
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ret float %sub
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}
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; CHECK-LABEL: @fsub_optnone
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; CHECK: alloca float
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; CHECK: alloca float
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; CHECK: store float
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; CHECK: store float
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; CHECK: load float
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; CHECK: load float
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; CHECK: fsub float
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; CHECK: ret float
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; typedef float __attribute__((ext_vector_type(4))) float4;
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; float4 vmul(float4 a, float4 b){ return a * b; }
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define <4 x float> @vmul_optimize(<4 x float> %a, <4 x float> %b) #0 {
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entry:
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%a.addr = alloca <4 x float>, align 16
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%b.addr = alloca <4 x float>, align 16
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store <4 x float> %a, <4 x float>* %a.addr, align 16
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store <4 x float> %b, <4 x float>* %b.addr, align 16
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%0 = load <4 x float>, <4 x float>* %a.addr, align 16
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%1 = load <4 x float>, <4 x float>* %b.addr, align 16
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%mul = fmul <4 x float> %0, %1
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ret <4 x float> %mul
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}
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; CHECK-LABEL: @vmul_optimize
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; CHECK-NOT: alloca
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; CHECK-NOT: store
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; CHECK-NOT: load
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; CHECK: ret
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define <4 x float> @vmul_optnone(<4 x float> %a, <4 x float> %b) #1 {
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entry:
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%a.addr = alloca <4 x float>, align 16
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%b.addr = alloca <4 x float>, align 16
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store <4 x float> %a, <4 x float>* %a.addr, align 16
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store <4 x float> %b, <4 x float>* %b.addr, align 16
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%0 = load <4 x float>, <4 x float>* %a.addr, align 16
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%1 = load <4 x float>, <4 x float>* %b.addr, align 16
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%mul = fmul <4 x float> %0, %1
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ret <4 x float> %mul
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}
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; CHECK-LABEL: @vmul_optnone
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; CHECK: alloca <4 x float>
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; CHECK: alloca <4 x float>
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; CHECK: store <4 x float>
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; CHECK: store <4 x float>
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; CHECK: load <4 x float>
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; CHECK: load <4 x float>
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; CHECK: fmul <4 x float>
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; CHECK: ret
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