forked from OSchip/llvm-project
148 lines
4.7 KiB
C++
148 lines
4.7 KiB
C++
//===-- SILowerI1Copies.cpp - Lower I1 Copies -----------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// i1 values are usually inserted by the CFG Structurize pass and they are
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/// unique in that they can be copied from VALU to SALU registers.
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/// This is not possible for any other value type. Since there are no
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/// MOV instructions for i1, we to use V_CMP_* and V_CNDMASK to move the i1.
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///
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//===----------------------------------------------------------------------===//
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//
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#define DEBUG_TYPE "si-i1-copies"
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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namespace {
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class SILowerI1Copies : public MachineFunctionPass {
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public:
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static char ID;
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public:
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SILowerI1Copies() : MachineFunctionPass(ID) {
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initializeSILowerI1CopiesPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "SI Lower il Copies";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineDominatorTree>();
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(SILowerI1Copies, DEBUG_TYPE,
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"SI Lower il Copies", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_END(SILowerI1Copies, DEBUG_TYPE,
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"SI Lower il Copies", false, false)
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char SILowerI1Copies::ID = 0;
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char &llvm::SILowerI1CopiesID = SILowerI1Copies::ID;
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FunctionPass *llvm::createSILowerI1CopiesPass() {
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return new SILowerI1Copies();
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}
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bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const SIInstrInfo *TII =
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static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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std::vector<unsigned> I1Defs;
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
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BI != BE; ++BI) {
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MachineBasicBlock &MBB = *BI;
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MachineBasicBlock::iterator I, Next;
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for (I = MBB.begin(); I != MBB.end(); I = Next) {
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Next = std::next(I);
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MachineInstr &MI = *I;
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if (MI.getOpcode() == AMDGPU::V_MOV_I1) {
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I1Defs.push_back(MI.getOperand(0).getReg());
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MI.setDesc(TII->get(AMDGPU::V_MOV_B32_e32));
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continue;
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}
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if (MI.getOpcode() == AMDGPU::V_AND_I1) {
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I1Defs.push_back(MI.getOperand(0).getReg());
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MI.setDesc(TII->get(AMDGPU::V_AND_B32_e32));
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continue;
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}
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if (MI.getOpcode() == AMDGPU::V_OR_I1) {
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I1Defs.push_back(MI.getOperand(0).getReg());
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MI.setDesc(TII->get(AMDGPU::V_OR_B32_e32));
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continue;
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}
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if (MI.getOpcode() == AMDGPU::V_XOR_I1) {
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I1Defs.push_back(MI.getOperand(0).getReg());
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MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e32));
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continue;
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}
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if (MI.getOpcode() != AMDGPU::COPY ||
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!TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg()) ||
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!TargetRegisterInfo::isVirtualRegister(MI.getOperand(1).getReg()))
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continue;
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const TargetRegisterClass *DstRC =
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MRI.getRegClass(MI.getOperand(0).getReg());
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const TargetRegisterClass *SrcRC =
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MRI.getRegClass(MI.getOperand(1).getReg());
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if (DstRC == &AMDGPU::VReg_1RegClass &&
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TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) {
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I1Defs.push_back(MI.getOperand(0).getReg());
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BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CNDMASK_B32_e64))
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.addOperand(MI.getOperand(0))
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.addImm(0)
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.addImm(-1)
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.addOperand(MI.getOperand(1));
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MI.eraseFromParent();
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} else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
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SrcRC == &AMDGPU::VReg_1RegClass) {
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BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CMP_NE_I32_e64))
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.addOperand(MI.getOperand(0))
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.addOperand(MI.getOperand(1))
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.addImm(0);
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MI.eraseFromParent();
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}
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}
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}
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for (unsigned Reg : I1Defs)
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MRI.setRegClass(Reg, &AMDGPU::VReg_32RegClass);
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return false;
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}
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