forked from OSchip/llvm-project
443 lines
12 KiB
C++
443 lines
12 KiB
C++
//===- RISCV.cpp ----------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "InputFiles.h"
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#include "SyntheticSections.h"
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#include "Target.h"
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using namespace llvm;
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using namespace llvm::object;
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using namespace llvm::support::endian;
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using namespace llvm::ELF;
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using namespace lld;
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using namespace lld::elf;
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namespace {
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class RISCV final : public TargetInfo {
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public:
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RISCV();
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uint32_t calcEFlags() const override;
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void writeGotHeader(uint8_t *buf) const override;
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void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
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void writePltHeader(uint8_t *buf) const override;
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void writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, uint64_t pltEntryAddr,
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int32_t index, unsigned relOff) const override;
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RelType getDynRel(RelType type) const override;
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RelExpr getRelExpr(RelType type, const Symbol &s,
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const uint8_t *loc) const override;
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void relocateOne(uint8_t *loc, RelType type, uint64_t val) const override;
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};
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} // end anonymous namespace
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const uint64_t dtpOffset = 0x800;
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enum Op {
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ADDI = 0x13,
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AUIPC = 0x17,
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JALR = 0x67,
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LD = 0x3003,
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LW = 0x2003,
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SRLI = 0x5013,
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SUB = 0x40000033,
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};
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enum Reg {
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X_RA = 1,
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X_T0 = 5,
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X_T1 = 6,
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X_T2 = 7,
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X_T3 = 28,
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};
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static uint32_t hi20(uint32_t val) { return (val + 0x800) >> 12; }
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static uint32_t lo12(uint32_t val) { return val & 4095; }
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static uint32_t itype(uint32_t op, uint32_t rd, uint32_t rs1, uint32_t imm) {
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return op | (rd << 7) | (rs1 << 15) | (imm << 20);
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}
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static uint32_t rtype(uint32_t op, uint32_t rd, uint32_t rs1, uint32_t rs2) {
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return op | (rd << 7) | (rs1 << 15) | (rs2 << 20);
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}
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static uint32_t utype(uint32_t op, uint32_t rd, uint32_t imm) {
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return op | (rd << 7) | (imm << 12);
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}
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RISCV::RISCV() {
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copyRel = R_RISCV_COPY;
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noneRel = R_RISCV_NONE;
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pltRel = R_RISCV_JUMP_SLOT;
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relativeRel = R_RISCV_RELATIVE;
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if (config->is64) {
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symbolicRel = R_RISCV_64;
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tlsModuleIndexRel = R_RISCV_TLS_DTPMOD64;
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tlsOffsetRel = R_RISCV_TLS_DTPREL64;
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tlsGotRel = R_RISCV_TLS_TPREL64;
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} else {
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symbolicRel = R_RISCV_32;
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tlsModuleIndexRel = R_RISCV_TLS_DTPMOD32;
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tlsOffsetRel = R_RISCV_TLS_DTPREL32;
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tlsGotRel = R_RISCV_TLS_TPREL32;
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}
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gotRel = symbolicRel;
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// .got[0] = _DYNAMIC
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gotBaseSymInGotPlt = false;
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gotHeaderEntriesNum = 1;
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// .got.plt[0] = _dl_runtime_resolve, .got.plt[1] = link_map
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gotPltHeaderEntriesNum = 2;
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pltEntrySize = 16;
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pltHeaderSize = 32;
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}
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static uint32_t getEFlags(InputFile *f) {
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if (config->is64)
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return cast<ObjFile<ELF64LE>>(f)->getObj().getHeader()->e_flags;
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return cast<ObjFile<ELF32LE>>(f)->getObj().getHeader()->e_flags;
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}
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uint32_t RISCV::calcEFlags() const {
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assert(!objectFiles.empty());
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uint32_t target = getEFlags(objectFiles.front());
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for (InputFile *f : objectFiles) {
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uint32_t eflags = getEFlags(f);
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if (eflags & EF_RISCV_RVC)
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target |= EF_RISCV_RVC;
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if ((eflags & EF_RISCV_FLOAT_ABI) != (target & EF_RISCV_FLOAT_ABI))
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error(toString(f) +
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": cannot link object files with different floating-point ABI");
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if ((eflags & EF_RISCV_RVE) != (target & EF_RISCV_RVE))
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error(toString(f) +
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": cannot link object files with different EF_RISCV_RVE");
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}
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return target;
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}
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void RISCV::writeGotHeader(uint8_t *buf) const {
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if (config->is64)
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write64le(buf, mainPart->dynamic->getVA());
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else
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write32le(buf, mainPart->dynamic->getVA());
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}
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void RISCV::writeGotPlt(uint8_t *buf, const Symbol &s) const {
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if (config->is64)
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write64le(buf, in.plt->getVA());
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else
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write32le(buf, in.plt->getVA());
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}
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void RISCV::writePltHeader(uint8_t *buf) const {
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// 1: auipc t2, %pcrel_hi(.got.plt)
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// sub t1, t1, t3
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// l[wd] t3, %pcrel_lo(1b)(t2); t3 = _dl_runtime_resolve
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// addi t1, t1, -pltHeaderSize-12; t1 = &.plt[i] - &.plt[0]
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// addi t0, t2, %pcrel_lo(1b)
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// srli t1, t1, (rv64?1:2); t1 = &.got.plt[i] - &.got.plt[0]
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// l[wd] t0, Wordsize(t0); t0 = link_map
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// jr t3
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uint32_t offset = in.gotPlt->getVA() - in.plt->getVA();
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uint32_t load = config->is64 ? LD : LW;
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write32le(buf + 0, utype(AUIPC, X_T2, hi20(offset)));
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write32le(buf + 4, rtype(SUB, X_T1, X_T1, X_T3));
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write32le(buf + 8, itype(load, X_T3, X_T2, lo12(offset)));
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write32le(buf + 12, itype(ADDI, X_T1, X_T1, -target->pltHeaderSize - 12));
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write32le(buf + 16, itype(ADDI, X_T0, X_T2, lo12(offset)));
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write32le(buf + 20, itype(SRLI, X_T1, X_T1, config->is64 ? 1 : 2));
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write32le(buf + 24, itype(load, X_T0, X_T0, config->wordsize));
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write32le(buf + 28, itype(JALR, 0, X_T3, 0));
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}
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void RISCV::writePlt(uint8_t *buf, uint64_t gotPltEntryAddr,
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uint64_t pltEntryAddr, int32_t index,
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unsigned relOff) const {
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// 1: auipc t3, %pcrel_hi(f@.got.plt)
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// l[wd] t3, %pcrel_lo(1b)(t3)
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// jalr t1, t3
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// nop
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uint32_t offset = gotPltEntryAddr - pltEntryAddr;
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write32le(buf + 0, utype(AUIPC, X_T3, hi20(offset)));
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write32le(buf + 4, itype(config->is64 ? LD : LW, X_T3, X_T3, lo12(offset)));
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write32le(buf + 8, itype(JALR, X_T1, X_T3, 0));
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write32le(buf + 12, itype(ADDI, 0, 0, 0));
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}
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RelType RISCV::getDynRel(RelType type) const {
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return type == target->symbolicRel ? type
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: static_cast<RelType>(R_RISCV_NONE);
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}
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RelExpr RISCV::getRelExpr(const RelType type, const Symbol &s,
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const uint8_t *loc) const {
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switch (type) {
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case R_RISCV_ADD8:
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case R_RISCV_ADD16:
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case R_RISCV_ADD32:
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case R_RISCV_ADD64:
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case R_RISCV_SET6:
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case R_RISCV_SET8:
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case R_RISCV_SET16:
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case R_RISCV_SET32:
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case R_RISCV_SUB6:
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case R_RISCV_SUB8:
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case R_RISCV_SUB16:
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case R_RISCV_SUB32:
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case R_RISCV_SUB64:
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return R_RISCV_ADD;
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case R_RISCV_JAL:
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case R_RISCV_BRANCH:
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case R_RISCV_PCREL_HI20:
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case R_RISCV_RVC_BRANCH:
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case R_RISCV_RVC_JUMP:
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case R_RISCV_32_PCREL:
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return R_PC;
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case R_RISCV_CALL:
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case R_RISCV_CALL_PLT:
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return R_PLT_PC;
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case R_RISCV_GOT_HI20:
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return R_GOT_PC;
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case R_RISCV_PCREL_LO12_I:
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case R_RISCV_PCREL_LO12_S:
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return R_RISCV_PC_INDIRECT;
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case R_RISCV_TLS_GD_HI20:
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return R_TLSGD_PC;
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case R_RISCV_TLS_GOT_HI20:
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config->hasStaticTlsModel = true;
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return R_GOT_PC;
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case R_RISCV_TPREL_HI20:
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case R_RISCV_TPREL_LO12_I:
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case R_RISCV_TPREL_LO12_S:
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return R_TLS;
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case R_RISCV_RELAX:
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case R_RISCV_ALIGN:
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case R_RISCV_TPREL_ADD:
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return R_HINT;
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default:
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return R_ABS;
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}
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}
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// Extract bits V[Begin:End], where range is inclusive, and Begin must be < 63.
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static uint32_t extractBits(uint64_t v, uint32_t begin, uint32_t end) {
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return (v & ((1ULL << (begin + 1)) - 1)) >> end;
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}
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void RISCV::relocateOne(uint8_t *loc, const RelType type,
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const uint64_t val) const {
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const unsigned bits = config->wordsize * 8;
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switch (type) {
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case R_RISCV_32:
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write32le(loc, val);
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return;
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case R_RISCV_64:
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write64le(loc, val);
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return;
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case R_RISCV_RVC_BRANCH: {
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checkInt(loc, static_cast<int64_t>(val) >> 1, 8, type);
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checkAlignment(loc, val, 2, type);
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uint16_t insn = read16le(loc) & 0xE383;
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uint16_t imm8 = extractBits(val, 8, 8) << 12;
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uint16_t imm4_3 = extractBits(val, 4, 3) << 10;
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uint16_t imm7_6 = extractBits(val, 7, 6) << 5;
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uint16_t imm2_1 = extractBits(val, 2, 1) << 3;
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uint16_t imm5 = extractBits(val, 5, 5) << 2;
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insn |= imm8 | imm4_3 | imm7_6 | imm2_1 | imm5;
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write16le(loc, insn);
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return;
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}
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case R_RISCV_RVC_JUMP: {
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checkInt(loc, static_cast<int64_t>(val) >> 1, 11, type);
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checkAlignment(loc, val, 2, type);
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uint16_t insn = read16le(loc) & 0xE003;
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uint16_t imm11 = extractBits(val, 11, 11) << 12;
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uint16_t imm4 = extractBits(val, 4, 4) << 11;
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uint16_t imm9_8 = extractBits(val, 9, 8) << 9;
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uint16_t imm10 = extractBits(val, 10, 10) << 8;
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uint16_t imm6 = extractBits(val, 6, 6) << 7;
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uint16_t imm7 = extractBits(val, 7, 7) << 6;
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uint16_t imm3_1 = extractBits(val, 3, 1) << 3;
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uint16_t imm5 = extractBits(val, 5, 5) << 2;
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insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5;
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write16le(loc, insn);
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return;
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}
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case R_RISCV_RVC_LUI: {
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int64_t imm = SignExtend64(val + 0x800, bits) >> 12;
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checkInt(loc, imm, 6, type);
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if (imm == 0) { // `c.lui rd, 0` is illegal, convert to `c.li rd, 0`
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write16le(loc, (read16le(loc) & 0x0F83) | 0x4000);
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} else {
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uint16_t imm17 = extractBits(val + 0x800, 17, 17) << 12;
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uint16_t imm16_12 = extractBits(val + 0x800, 16, 12) << 2;
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write16le(loc, (read16le(loc) & 0xEF83) | imm17 | imm16_12);
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}
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return;
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}
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case R_RISCV_JAL: {
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checkInt(loc, static_cast<int64_t>(val) >> 1, 20, type);
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checkAlignment(loc, val, 2, type);
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uint32_t insn = read32le(loc) & 0xFFF;
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uint32_t imm20 = extractBits(val, 20, 20) << 31;
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uint32_t imm10_1 = extractBits(val, 10, 1) << 21;
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uint32_t imm11 = extractBits(val, 11, 11) << 20;
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uint32_t imm19_12 = extractBits(val, 19, 12) << 12;
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insn |= imm20 | imm10_1 | imm11 | imm19_12;
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write32le(loc, insn);
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return;
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}
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case R_RISCV_BRANCH: {
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checkInt(loc, static_cast<int64_t>(val) >> 1, 12, type);
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checkAlignment(loc, val, 2, type);
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uint32_t insn = read32le(loc) & 0x1FFF07F;
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uint32_t imm12 = extractBits(val, 12, 12) << 31;
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uint32_t imm10_5 = extractBits(val, 10, 5) << 25;
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uint32_t imm4_1 = extractBits(val, 4, 1) << 8;
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uint32_t imm11 = extractBits(val, 11, 11) << 7;
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insn |= imm12 | imm10_5 | imm4_1 | imm11;
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write32le(loc, insn);
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return;
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}
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// auipc + jalr pair
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case R_RISCV_CALL:
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case R_RISCV_CALL_PLT: {
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int64_t hi = SignExtend64(val + 0x800, bits) >> 12;
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checkInt(loc, hi, 20, type);
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if (isInt<20>(hi)) {
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relocateOne(loc, R_RISCV_PCREL_HI20, val);
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relocateOne(loc + 4, R_RISCV_PCREL_LO12_I, val);
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}
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return;
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}
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case R_RISCV_GOT_HI20:
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case R_RISCV_PCREL_HI20:
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case R_RISCV_TLS_GD_HI20:
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case R_RISCV_TLS_GOT_HI20:
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case R_RISCV_TPREL_HI20:
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case R_RISCV_HI20: {
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uint64_t hi = val + 0x800;
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checkInt(loc, SignExtend64(hi, bits) >> 12, 20, type);
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write32le(loc, (read32le(loc) & 0xFFF) | (hi & 0xFFFFF000));
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return;
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}
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case R_RISCV_PCREL_LO12_I:
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case R_RISCV_TPREL_LO12_I:
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case R_RISCV_LO12_I: {
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uint64_t hi = (val + 0x800) >> 12;
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uint64_t lo = val - (hi << 12);
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write32le(loc, (read32le(loc) & 0xFFFFF) | ((lo & 0xFFF) << 20));
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return;
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}
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case R_RISCV_PCREL_LO12_S:
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case R_RISCV_TPREL_LO12_S:
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case R_RISCV_LO12_S: {
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uint64_t hi = (val + 0x800) >> 12;
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uint64_t lo = val - (hi << 12);
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uint32_t imm11_5 = extractBits(lo, 11, 5) << 25;
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uint32_t imm4_0 = extractBits(lo, 4, 0) << 7;
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write32le(loc, (read32le(loc) & 0x1FFF07F) | imm11_5 | imm4_0);
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return;
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}
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case R_RISCV_ADD8:
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*loc += val;
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return;
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case R_RISCV_ADD16:
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write16le(loc, read16le(loc) + val);
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return;
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case R_RISCV_ADD32:
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write32le(loc, read32le(loc) + val);
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return;
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case R_RISCV_ADD64:
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write64le(loc, read64le(loc) + val);
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return;
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case R_RISCV_SUB6:
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*loc = (*loc & 0xc0) | (((*loc & 0x3f) - val) & 0x3f);
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return;
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case R_RISCV_SUB8:
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*loc -= val;
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return;
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case R_RISCV_SUB16:
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write16le(loc, read16le(loc) - val);
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return;
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case R_RISCV_SUB32:
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write32le(loc, read32le(loc) - val);
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return;
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case R_RISCV_SUB64:
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write64le(loc, read64le(loc) - val);
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return;
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case R_RISCV_SET6:
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*loc = (*loc & 0xc0) | (val & 0x3f);
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return;
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case R_RISCV_SET8:
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*loc = val;
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return;
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case R_RISCV_SET16:
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write16le(loc, val);
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return;
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case R_RISCV_SET32:
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case R_RISCV_32_PCREL:
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write32le(loc, val);
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return;
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case R_RISCV_TLS_DTPREL32:
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write32le(loc, val - dtpOffset);
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break;
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case R_RISCV_TLS_DTPREL64:
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write64le(loc, val - dtpOffset);
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break;
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case R_RISCV_ALIGN:
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case R_RISCV_RELAX:
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return; // Ignored (for now)
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case R_RISCV_NONE:
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return; // Do nothing
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// These are handled by the dynamic linker
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case R_RISCV_RELATIVE:
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case R_RISCV_COPY:
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case R_RISCV_JUMP_SLOT:
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// GP-relative relocations are only produced after relaxation, which
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// we don't support for now
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case R_RISCV_GPREL_I:
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case R_RISCV_GPREL_S:
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default:
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error(getErrorLocation(loc) +
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"unimplemented relocation: " + toString(type));
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return;
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}
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|
}
|
|
|
|
TargetInfo *elf::getRISCVTargetInfo() {
|
|
static RISCV target;
|
|
return ⌖
|
|
}
|