forked from OSchip/llvm-project
64 lines
1.9 KiB
LLVM
64 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686--
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; RUN: llc -pre-RA-sched=source < %s -mtriple=i686-unknown-linux -mcpu=corei7 | FileCheck %s --check-prefix=SOURCE-SCHED
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; PR2748
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@g_73 = external global i32
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@g_5 = external global i32
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define i32 @func_44(i16 signext %p_46) nounwind {
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; SOURCE-SCHED-LABEL: func_44:
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; SOURCE-SCHED: # %bb.0: # %entry
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; SOURCE-SCHED-NEXT: subl $12, %esp
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; SOURCE-SCHED-NEXT: movl g_5, %eax
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; SOURCE-SCHED-NEXT: sarl %eax
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; SOURCE-SCHED-NEXT: xorl %ecx, %ecx
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; SOURCE-SCHED-NEXT: cmpl $1, %eax
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; SOURCE-SCHED-NEXT: setg %cl
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; SOURCE-SCHED-NEXT: movb g_73, %dl
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; SOURCE-SCHED-NEXT: xorl %eax, %eax
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; SOURCE-SCHED-NEXT: subb {{[0-9]+}}(%esp), %al
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; SOURCE-SCHED-NEXT: testb %dl, %dl
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; SOURCE-SCHED-NEXT: jne .LBB0_2
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; SOURCE-SCHED-NEXT: # %bb.1: # %bb11
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; SOURCE-SCHED-NEXT: movzbl %al, %eax
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; SOURCE-SCHED-NEXT: divb %dl
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; SOURCE-SCHED-NEXT: movzbl %ah, %eax
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; SOURCE-SCHED-NEXT: .LBB0_2: # %bb12
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; SOURCE-SCHED-NEXT: xorl %edx, %edx
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; SOURCE-SCHED-NEXT: testb %al, %al
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; SOURCE-SCHED-NEXT: setne %dl
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; SOURCE-SCHED-NEXT: subl $4, %esp
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; SOURCE-SCHED-NEXT: pushl $0
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; SOURCE-SCHED-NEXT: pushl %ecx
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; SOURCE-SCHED-NEXT: pushl %edx
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; SOURCE-SCHED-NEXT: calll func_48
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; SOURCE-SCHED-NEXT: addl $28, %esp
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; SOURCE-SCHED-NEXT: retl
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entry:
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%0 = load i32, i32* @g_5, align 4
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%1 = ashr i32 %0, 1
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%2 = icmp sgt i32 %1, 1
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%3 = zext i1 %2 to i32
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%4 = load i32, i32* @g_73, align 4
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%5 = zext i16 %p_46 to i64
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%6 = sub i64 0, %5
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%7 = trunc i64 %6 to i8
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%8 = trunc i32 %4 to i8
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%9 = icmp eq i8 %8, 0
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br i1 %9, label %bb11, label %bb12
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bb11:
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%10 = urem i8 %7, %8
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br label %bb12
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bb12:
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%.014.in = phi i8 [ %10, %bb11 ], [ %7, %entry ]
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%11 = icmp ne i8 %.014.in, 0
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%12 = zext i1 %11 to i32
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%13 = tail call i32 (...) @func_48( i32 %12, i32 %3, i32 0 ) nounwind
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ret i32 undef
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}
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declare i32 @func_48(...)
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