forked from OSchip/llvm-project
167 lines
4.4 KiB
C++
167 lines
4.4 KiB
C++
#include "ARMBaseInstrInfo.h"
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#include "ARMSubtarget.h"
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#include "ARMTargetMachine.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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// Test for instructions that aren't immediately obviously valid within a
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// tail-predicated loop. This should be marked up in their tablegen
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// descriptions. Currently the horizontal vector operations are tagged.
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// TODO Add instructions that perform:
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// - truncation,
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// - extensions,
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// - byte swapping,
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// - others?
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TEST(MachineInstrInvalidTailPredication, IsCorrect) {
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LLVMInitializeARMTargetInfo();
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LLVMInitializeARMTarget();
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LLVMInitializeARMTargetMC();
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auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
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std::string Error;
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const Target *T = TargetRegistry::lookupTarget(TT, Error);
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if (!T) {
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dbgs() << Error;
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return;
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}
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TargetOptions Options;
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auto TM = std::unique_ptr<LLVMTargetMachine>(
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static_cast<LLVMTargetMachine*>(
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T->createTargetMachine(TT, "generic", "", Options, None, None,
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CodeGenOpt::Default)));
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auto MII = TM->getMCInstrInfo();
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using namespace ARM;
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auto IsInvalidTPOpcode = [](unsigned Opcode) {
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switch (Opcode) {
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case MVE_VABAVs8:
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case MVE_VABAVs16:
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case MVE_VABAVs32:
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case MVE_VABAVu8:
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case MVE_VABAVu16:
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case MVE_VABAVu32:
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case MVE_VADDVs8acc:
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case MVE_VADDVs16acc:
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case MVE_VADDVs32acc:
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case MVE_VADDVu8acc:
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case MVE_VADDVu16acc:
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case MVE_VADDVu32acc:
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case MVE_VADDVs8no_acc:
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case MVE_VADDVs16no_acc:
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case MVE_VADDVs32no_acc:
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case MVE_VADDVu8no_acc:
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case MVE_VADDVu16no_acc:
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case MVE_VADDVu32no_acc:
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case MVE_VADDLVs32no_acc:
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case MVE_VADDLVu32no_acc:
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case MVE_VADDLVs32acc:
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case MVE_VADDLVu32acc:
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case MVE_VMLADAVas16:
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case MVE_VMLADAVas32:
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case MVE_VMLADAVas8:
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case MVE_VMLADAVau16:
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case MVE_VMLADAVau32:
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case MVE_VMLADAVau8:
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case MVE_VMLADAVaxs16:
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case MVE_VMLADAVaxs32:
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case MVE_VMLADAVaxs8:
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case MVE_VMLADAVs16:
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case MVE_VMLADAVs32:
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case MVE_VMLADAVs8:
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case MVE_VMLADAVu16:
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case MVE_VMLADAVu32:
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case MVE_VMLADAVu8:
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case MVE_VMLADAVxs16:
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case MVE_VMLADAVxs32:
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case MVE_VMLADAVxs8:
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case MVE_VMLALDAVas16:
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case MVE_VMLALDAVas32:
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case MVE_VMLALDAVau16:
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case MVE_VMLALDAVau32:
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case MVE_VMLALDAVaxs16:
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case MVE_VMLALDAVaxs32:
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case MVE_VMLALDAVs16:
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case MVE_VMLALDAVs32:
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case MVE_VMLALDAVu16:
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case MVE_VMLALDAVu32:
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case MVE_VMLALDAVxs16:
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case MVE_VMLALDAVxs32:
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case MVE_VMLSDAVas16:
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case MVE_VMLSDAVas32:
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case MVE_VMLSDAVas8:
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case MVE_VMLSDAVaxs16:
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case MVE_VMLSDAVaxs32:
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case MVE_VMLSDAVaxs8:
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case MVE_VMLSDAVs16:
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case MVE_VMLSDAVs32:
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case MVE_VMLSDAVs8:
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case MVE_VMLSDAVxs16:
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case MVE_VMLSDAVxs32:
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case MVE_VMLSDAVxs8:
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case MVE_VMLSLDAVas16:
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case MVE_VMLSLDAVas32:
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case MVE_VMLSLDAVaxs16:
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case MVE_VMLSLDAVaxs32:
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case MVE_VMLSLDAVs16:
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case MVE_VMLSLDAVs32:
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case MVE_VMLSLDAVxs16:
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case MVE_VMLSLDAVxs32:
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case MVE_VRMLALDAVHas32:
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case MVE_VRMLALDAVHau32:
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case MVE_VRMLALDAVHaxs32:
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case MVE_VRMLALDAVHs32:
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case MVE_VRMLALDAVHu32:
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case MVE_VRMLALDAVHxs32:
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case MVE_VRMLSLDAVHas32:
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case MVE_VRMLSLDAVHaxs32:
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case MVE_VRMLSLDAVHs32:
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case MVE_VRMLSLDAVHxs32:
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case MVE_VMAXNMVf16:
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case MVE_VMINNMVf16:
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case MVE_VMAXNMVf32:
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case MVE_VMINNMVf32:
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case MVE_VMAXNMAVf16:
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case MVE_VMINNMAVf16:
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case MVE_VMAXNMAVf32:
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case MVE_VMINNMAVf32:
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case MVE_VMAXVs8:
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case MVE_VMAXVs16:
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case MVE_VMAXVs32:
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case MVE_VMAXVu8:
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case MVE_VMAXVu16:
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case MVE_VMAXVu32:
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case MVE_VMINVs8:
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case MVE_VMINVs16:
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case MVE_VMINVs32:
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case MVE_VMINVu8:
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case MVE_VMINVu16:
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case MVE_VMINVu32:
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case MVE_VMAXAVs8:
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case MVE_VMAXAVs16:
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case MVE_VMAXAVs32:
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case MVE_VMINAVs8:
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case MVE_VMINAVs16:
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case MVE_VMINAVs32:
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return true;
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default:
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return false;
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}
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};
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for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
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uint64_t Flags = MII->get(i).TSFlags;
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bool Invalid = (Flags & ARMII::InvalidForTailPredication) != 0;
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ASSERT_EQ(IsInvalidTPOpcode(i), Invalid)
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<< MII->getName(i)
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<< ": mismatched expectation for tail-predicated safety\n";
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}
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}
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