forked from OSchip/llvm-project
49 lines
1.2 KiB
LLVM
49 lines
1.2 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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; RUN: llc -O0 < %s | FileCheck %s -check-prefix=CHECK-O0
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-bgq-linux"
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; Function Attrs: nounwind
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define void @test_qpx() unnamed_addr #0 align 2 {
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entry:
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%0 = load i32, i32* undef, align 4
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%1 = trunc i32 %0 to i8
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call void @llvm.memset.p0i8.i64(i8* null, i8 %1, i64 64, i32 32, i1 false)
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ret void
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; CHECK-LABEL: @test_qpx
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; CHECK: qvstfdx
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; CHECK: qvstfdx
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; CHECK: blr
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; CHECK-O0-LABEL: @test_qpx
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; CHECK-O0-NOT: qvstfdx
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; CHECK-O0: blr
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}
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; Function Attrs: nounwind
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #1
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; Function Attrs: nounwind
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define void @test_vsx() unnamed_addr #2 align 2 {
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entry:
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%0 = load i32, i32* undef, align 4
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%1 = trunc i32 %0 to i8
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call void @llvm.memset.p0i8.i64(i8* null, i8 %1, i64 32, i32 1, i1 false)
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ret void
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; CHECK-LABEL: @test_vsx
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; CHECK: stxvw4x
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; CHECK: stxvw4x
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; CHECK: blr
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; CHECK-O0-LABEL: @test_vsx
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; CHECK-O0-NOT: stxvw4x
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; CHECK-O0: blr
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}
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attributes #0 = { nounwind "target-cpu"="a2q" }
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attributes #1 = { nounwind }
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attributes #2 = { nounwind "target-cpu"="pwr7" }
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