forked from OSchip/llvm-project
2710171a15
Summary: The symbols use the processor-specific SHN_AMDGPU_LDS section index introduced with a previous change. The linker is then expected to resolve relocations, which are also emitted. Initially disabled for HSA and PAL environments until they have caught up in terms of linker and runtime loader. Some notes: - The llvm.amdgcn.groupstaticsize intrinsics can no longer be lowered to a constant at compile times, which means some tests can no longer be applied. The current "solution" is a terrible hack, but the intrinsic isn't used by Mesa, so we can keep it for now. - We no longer know the full LDS size per kernel at compile time, which means that we can no longer generate a relevant error message at compile time. It would be possible to add a check for the size of individual variables, but ultimately the linker will have to perform the final check. Change-Id: If66dbf33fccfbf3609aefefa2558ac0850d42275 Reviewers: arsenm, rampitec, t-tye, b-sumner, jsjodin Subscribers: qcolombet, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61494 llvm-svn: 364297 |
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| .. | ||
| expected-target-index-name.mir | ||
| intrinsics.mir | ||
| invalid-target-index-operand.mir | ||
| lit.local.cfg | ||
| load-store-opt-dlc.mir | ||
| machine-function-info-no-ir.mir | ||
| machine-function-info-register-parse-error1.mir | ||
| machine-function-info-register-parse-error2.mir | ||
| machine-function-info.ll | ||
| mfi-frame-offset-reg-class.mir | ||
| mfi-parse-error-frame-offset-reg.mir | ||
| mfi-parse-error-scratch-rsrc-reg.mir | ||
| mfi-parse-error-scratch-wave-offset-reg.mir | ||
| mfi-parse-error-stack-ptr-offset-reg.mir | ||
| mfi-scratch-rsrc-reg-reg-class.mir | ||
| mfi-scratch-wave-offset-reg-class.mir | ||
| mfi-stack-ptr-offset-reg-class.mir | ||
| mir-canon-multi.mir | ||
| parse-order-reserved-regs.mir | ||
| stack-id.mir | ||
| syncscopes.mir | ||
| target-flags.mir | ||
| target-index-operands.mir | ||