forked from OSchip/llvm-project
643 lines
20 KiB
C++
643 lines
20 KiB
C++
//===-- AMDILISelLowering.cpp - AMDIL DAG Lowering Implementation ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief TargetLowering functions borrowed from AMDIL.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUISelLowering.h"
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "AMDILIntrinsicInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// TargetLowering Implementation Help Functions End
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// TargetLowering Class Implementation Begins
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//===----------------------------------------------------------------------===//
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void AMDGPUTargetLowering::InitAMDILLowering() {
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static const int types[] = {
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(int)MVT::i8,
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(int)MVT::i16,
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(int)MVT::i32,
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(int)MVT::f32,
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(int)MVT::f64,
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(int)MVT::i64,
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(int)MVT::v2i8,
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(int)MVT::v4i8,
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(int)MVT::v2i16,
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(int)MVT::v4i16,
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(int)MVT::v4f32,
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(int)MVT::v4i32,
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(int)MVT::v2f32,
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(int)MVT::v2i32,
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(int)MVT::v2f64,
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(int)MVT::v2i64
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};
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static const int IntTypes[] = {
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(int)MVT::i8,
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(int)MVT::i16,
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(int)MVT::i32,
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(int)MVT::i64
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};
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static const int FloatTypes[] = {
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(int)MVT::f32,
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(int)MVT::f64
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};
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static const int VectorTypes[] = {
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(int)MVT::v2i8,
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(int)MVT::v4i8,
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(int)MVT::v2i16,
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(int)MVT::v4i16,
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(int)MVT::v4f32,
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(int)MVT::v4i32,
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(int)MVT::v2f32,
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(int)MVT::v2i32,
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(int)MVT::v2f64,
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(int)MVT::v2i64
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};
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const size_t NumTypes = array_lengthof(types);
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const size_t NumFloatTypes = array_lengthof(FloatTypes);
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const size_t NumIntTypes = array_lengthof(IntTypes);
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const size_t NumVectorTypes = array_lengthof(VectorTypes);
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const AMDGPUSubtarget &STM = getTargetMachine().getSubtarget<AMDGPUSubtarget>();
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// These are the current register classes that are
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// supported
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for (unsigned int x = 0; x < NumTypes; ++x) {
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MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
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//FIXME: SIGN_EXTEND_INREG is not meaningful for floating point types
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// We cannot sextinreg, expand to shifts
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setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
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setOperationAction(ISD::SUBE, VT, Expand);
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setOperationAction(ISD::SUBC, VT, Expand);
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setOperationAction(ISD::ADDE, VT, Expand);
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setOperationAction(ISD::ADDC, VT, Expand);
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setOperationAction(ISD::BRCOND, VT, Custom);
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setOperationAction(ISD::BR_JT, VT, Expand);
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setOperationAction(ISD::BRIND, VT, Expand);
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// TODO: Implement custom UREM/SREM routines
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setOperationAction(ISD::SREM, VT, Expand);
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setOperationAction(ISD::SMUL_LOHI, VT, Expand);
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setOperationAction(ISD::UMUL_LOHI, VT, Expand);
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if (VT != MVT::i64 && VT != MVT::v2i64) {
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setOperationAction(ISD::SDIV, VT, Custom);
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}
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}
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for (unsigned int x = 0; x < NumFloatTypes; ++x) {
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MVT::SimpleValueType VT = (MVT::SimpleValueType)FloatTypes[x];
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// IL does not have these operations for floating point types
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setOperationAction(ISD::FP_ROUND_INREG, VT, Expand);
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setOperationAction(ISD::SETOLT, VT, Expand);
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setOperationAction(ISD::SETOGE, VT, Expand);
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setOperationAction(ISD::SETOGT, VT, Expand);
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setOperationAction(ISD::SETOLE, VT, Expand);
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setOperationAction(ISD::SETULT, VT, Expand);
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setOperationAction(ISD::SETUGE, VT, Expand);
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setOperationAction(ISD::SETUGT, VT, Expand);
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setOperationAction(ISD::SETULE, VT, Expand);
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}
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for (unsigned int x = 0; x < NumIntTypes; ++x) {
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MVT::SimpleValueType VT = (MVT::SimpleValueType)IntTypes[x];
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// GPU also does not have divrem function for signed or unsigned
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setOperationAction(ISD::SDIVREM, VT, Expand);
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// GPU does not have [S|U]MUL_LOHI functions as a single instruction
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setOperationAction(ISD::SMUL_LOHI, VT, Expand);
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setOperationAction(ISD::UMUL_LOHI, VT, Expand);
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setOperationAction(ISD::BSWAP, VT, Expand);
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// GPU doesn't have any counting operators
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setOperationAction(ISD::CTPOP, VT, Expand);
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setOperationAction(ISD::CTTZ, VT, Expand);
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setOperationAction(ISD::CTLZ, VT, Expand);
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}
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for (unsigned int ii = 0; ii < NumVectorTypes; ++ii) {
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MVT::SimpleValueType VT = (MVT::SimpleValueType)VectorTypes[ii];
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
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setOperationAction(ISD::SDIVREM, VT, Expand);
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setOperationAction(ISD::SMUL_LOHI, VT, Expand);
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// setOperationAction(ISD::VSETCC, VT, Expand);
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setOperationAction(ISD::SELECT_CC, VT, Expand);
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}
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setOperationAction(ISD::MULHU, MVT::i64, Expand);
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setOperationAction(ISD::MULHU, MVT::v2i64, Expand);
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setOperationAction(ISD::MULHS, MVT::i64, Expand);
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setOperationAction(ISD::MULHS, MVT::v2i64, Expand);
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setOperationAction(ISD::ADD, MVT::v2i64, Expand);
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setOperationAction(ISD::SREM, MVT::v2i64, Expand);
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setOperationAction(ISD::Constant , MVT::i64 , Legal);
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setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
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setOperationAction(ISD::TRUNCATE, MVT::v2i64, Expand);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expand);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v2i64, Expand);
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setOperationAction(ISD::ANY_EXTEND, MVT::v2i64, Expand);
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if (STM.hasHWFP64()) {
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// we support loading/storing v2f64 but not operations on the type
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setOperationAction(ISD::FADD, MVT::v2f64, Expand);
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setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
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setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
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setOperationAction(ISD::FP_ROUND_INREG, MVT::v2f64, Expand);
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setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
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setOperationAction(ISD::ConstantFP , MVT::f64 , Legal);
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// We want to expand vector conversions into their scalar
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// counterparts.
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setOperationAction(ISD::TRUNCATE, MVT::v2f64, Expand);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expand);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v2f64, Expand);
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setOperationAction(ISD::ANY_EXTEND, MVT::v2f64, Expand);
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setOperationAction(ISD::FABS, MVT::f64, Expand);
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setOperationAction(ISD::FABS, MVT::v2f64, Expand);
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}
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// TODO: Fix the UDIV24 algorithm so it works for these
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// types correctly. This needs vector comparisons
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// for this to work correctly.
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setOperationAction(ISD::UDIV, MVT::v2i8, Expand);
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setOperationAction(ISD::UDIV, MVT::v4i8, Expand);
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setOperationAction(ISD::UDIV, MVT::v2i16, Expand);
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setOperationAction(ISD::UDIV, MVT::v4i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
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setOperationAction(ISD::SUBC, MVT::Other, Expand);
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setOperationAction(ISD::ADDE, MVT::Other, Expand);
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setOperationAction(ISD::ADDC, MVT::Other, Expand);
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BRIND, MVT::Other, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
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// Use the default implementation.
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setOperationAction(ISD::ConstantFP , MVT::f32 , Legal);
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setOperationAction(ISD::Constant , MVT::i32 , Legal);
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setSchedulingPreference(Sched::RegPressure);
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setPow2DivIsCheap(false);
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setSelectIsExpensive(true);
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setJumpIsExpensive(true);
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MaxStoresPerMemcpy = 4096;
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MaxStoresPerMemmove = 4096;
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MaxStoresPerMemset = 4096;
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}
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bool
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AMDGPUTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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const CallInst &I, unsigned Intrinsic) const {
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return false;
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}
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// The backend supports 32 and 64 bit floating point immediates
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bool
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AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
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if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32
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|| VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) {
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return true;
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} else {
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return false;
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}
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}
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bool
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AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
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if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32
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|| VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) {
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return false;
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} else {
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return true;
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}
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}
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// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
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// be zero. Op is expected to be a target specific node. Used by DAG
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// combiner.
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void
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AMDGPUTargetLowering::computeMaskedBitsForTargetNode(
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const SDValue Op,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth) const {
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APInt KnownZero2;
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APInt KnownOne2;
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KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything
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switch (Op.getOpcode()) {
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default: break;
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case ISD::SELECT_CC:
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DAG.ComputeMaskedBits(
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Op.getOperand(1),
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KnownZero,
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KnownOne,
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Depth + 1
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);
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DAG.ComputeMaskedBits(
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Op.getOperand(0),
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KnownZero2,
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KnownOne2
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);
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assert((KnownZero & KnownOne) == 0
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&& "Bits known to be one AND zero?");
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assert((KnownZero2 & KnownOne2) == 0
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&& "Bits known to be one AND zero?");
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// Only known if known in both the LHS and RHS
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KnownOne &= KnownOne2;
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KnownZero &= KnownZero2;
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break;
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};
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}
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//===----------------------------------------------------------------------===//
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// Other Lowering Hooks
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//===----------------------------------------------------------------------===//
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SDValue
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AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
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EVT OVT = Op.getValueType();
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SDValue DST;
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if (OVT.getScalarType() == MVT::i64) {
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DST = LowerSDIV64(Op, DAG);
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} else if (OVT.getScalarType() == MVT::i32) {
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DST = LowerSDIV32(Op, DAG);
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} else if (OVT.getScalarType() == MVT::i16
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|| OVT.getScalarType() == MVT::i8) {
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DST = LowerSDIV24(Op, DAG);
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} else {
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DST = SDValue(Op.getNode(), 0);
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}
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return DST;
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}
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SDValue
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AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const {
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EVT OVT = Op.getValueType();
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SDValue DST;
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if (OVT.getScalarType() == MVT::i64) {
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DST = LowerSREM64(Op, DAG);
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} else if (OVT.getScalarType() == MVT::i32) {
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DST = LowerSREM32(Op, DAG);
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} else if (OVT.getScalarType() == MVT::i16) {
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DST = LowerSREM16(Op, DAG);
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} else if (OVT.getScalarType() == MVT::i8) {
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DST = LowerSREM8(Op, DAG);
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} else {
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DST = SDValue(Op.getNode(), 0);
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}
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return DST;
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}
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SDValue
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AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const {
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SDValue Data = Op.getOperand(0);
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VTSDNode *BaseType = cast<VTSDNode>(Op.getOperand(1));
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SDLoc DL(Op);
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EVT DVT = Data.getValueType();
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EVT BVT = BaseType->getVT();
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unsigned baseBits = BVT.getScalarType().getSizeInBits();
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unsigned srcBits = DVT.isSimple() ? DVT.getScalarType().getSizeInBits() : 1;
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unsigned shiftBits = srcBits - baseBits;
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if (srcBits < 32) {
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// If the op is less than 32 bits, then it needs to extend to 32bits
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// so it can properly keep the upper bits valid.
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EVT IVT = genIntType(32, DVT.isVector() ? DVT.getVectorNumElements() : 1);
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Data = DAG.getNode(ISD::ZERO_EXTEND, DL, IVT, Data);
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shiftBits = 32 - baseBits;
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DVT = IVT;
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}
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SDValue Shift = DAG.getConstant(shiftBits, DVT);
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// Shift left by 'Shift' bits.
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Data = DAG.getNode(ISD::SHL, DL, DVT, Data, Shift);
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// Signed shift Right by 'Shift' bits.
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Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);
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if (srcBits < 32) {
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// Once the sign extension is done, the op needs to be converted to
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// its original type.
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Data = DAG.getSExtOrTrunc(Data, DL, Op.getOperand(0).getValueType());
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}
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return Data;
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}
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EVT
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AMDGPUTargetLowering::genIntType(uint32_t size, uint32_t numEle) const {
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int iSize = (size * numEle);
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int vEle = (iSize >> ((size == 64) ? 6 : 5));
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if (!vEle) {
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vEle = 1;
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}
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if (size == 64) {
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if (vEle == 1) {
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return EVT(MVT::i64);
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} else {
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return EVT(MVT::getVectorVT(MVT::i64, vEle));
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}
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} else {
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if (vEle == 1) {
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return EVT(MVT::i32);
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} else {
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return EVT(MVT::getVectorVT(MVT::i32, vEle));
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}
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}
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}
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SDValue
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AMDGPUTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
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SDValue Chain = Op.getOperand(0);
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SDValue Cond = Op.getOperand(1);
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SDValue Jump = Op.getOperand(2);
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SDValue Result;
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Result = DAG.getNode(
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AMDGPUISD::BRANCH_COND,
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SDLoc(Op),
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Op.getValueType(),
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Chain, Jump, Cond);
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return Result;
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}
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SDValue
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AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const {
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SDLoc DL(Op);
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EVT OVT = Op.getValueType();
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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MVT INTTY;
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MVT FLTTY;
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if (!OVT.isVector()) {
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INTTY = MVT::i32;
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FLTTY = MVT::f32;
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} else if (OVT.getVectorNumElements() == 2) {
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INTTY = MVT::v2i32;
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FLTTY = MVT::v2f32;
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} else if (OVT.getVectorNumElements() == 4) {
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INTTY = MVT::v4i32;
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FLTTY = MVT::v4f32;
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}
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unsigned bitsize = OVT.getScalarType().getSizeInBits();
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// char|short jq = ia ^ ib;
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SDValue jq = DAG.getNode(ISD::XOR, DL, OVT, LHS, RHS);
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// jq = jq >> (bitsize - 2)
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jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
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// jq = jq | 0x1
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jq = DAG.getNode(ISD::OR, DL, OVT, jq, DAG.getConstant(1, OVT));
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// jq = (int)jq
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jq = DAG.getSExtOrTrunc(jq, DL, INTTY);
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// int ia = (int)LHS;
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SDValue ia = DAG.getSExtOrTrunc(LHS, DL, INTTY);
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// int ib, (int)RHS;
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SDValue ib = DAG.getSExtOrTrunc(RHS, DL, INTTY);
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// float fa = (float)ia;
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SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);
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// float fb = (float)ib;
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SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
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// float fq = native_divide(fa, fb);
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SDValue fq = DAG.getNode(AMDGPUISD::DIV_INF, DL, FLTTY, fa, fb);
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// fq = trunc(fq);
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fq = DAG.getNode(ISD::FTRUNC, DL, FLTTY, fq);
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// float fqneg = -fq;
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SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq);
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|
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// float fr = mad(fqneg, fb, fa);
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SDValue fr = DAG.getNode(ISD::FADD, DL, FLTTY,
|
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DAG.getNode(ISD::MUL, DL, FLTTY, fqneg, fb), fa);
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|
|
|
// int iq = (int)fq;
|
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SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);
|
|
|
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// fr = fabs(fr);
|
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fr = DAG.getNode(ISD::FABS, DL, FLTTY, fr);
|
|
|
|
// fb = fabs(fb);
|
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fb = DAG.getNode(ISD::FABS, DL, FLTTY, fb);
|
|
|
|
// int cv = fr >= fb;
|
|
SDValue cv;
|
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if (INTTY == MVT::i32) {
|
|
cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
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|
} else {
|
|
cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
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}
|
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// jq = (cv ? jq : 0);
|
|
jq = DAG.getNode(ISD::SELECT, DL, OVT, cv, jq,
|
|
DAG.getConstant(0, OVT));
|
|
// dst = iq + jq;
|
|
iq = DAG.getSExtOrTrunc(iq, DL, OVT);
|
|
iq = DAG.getNode(ISD::ADD, DL, OVT, iq, jq);
|
|
return iq;
|
|
}
|
|
|
|
SDValue
|
|
AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const {
|
|
SDLoc DL(Op);
|
|
EVT OVT = Op.getValueType();
|
|
SDValue LHS = Op.getOperand(0);
|
|
SDValue RHS = Op.getOperand(1);
|
|
// The LowerSDIV32 function generates equivalent to the following IL.
|
|
// mov r0, LHS
|
|
// mov r1, RHS
|
|
// ilt r10, r0, 0
|
|
// ilt r11, r1, 0
|
|
// iadd r0, r0, r10
|
|
// iadd r1, r1, r11
|
|
// ixor r0, r0, r10
|
|
// ixor r1, r1, r11
|
|
// udiv r0, r0, r1
|
|
// ixor r10, r10, r11
|
|
// iadd r0, r0, r10
|
|
// ixor DST, r0, r10
|
|
|
|
// mov r0, LHS
|
|
SDValue r0 = LHS;
|
|
|
|
// mov r1, RHS
|
|
SDValue r1 = RHS;
|
|
|
|
// ilt r10, r0, 0
|
|
SDValue r10 = DAG.getSelectCC(DL,
|
|
r0, DAG.getConstant(0, OVT),
|
|
DAG.getConstant(-1, MVT::i32),
|
|
DAG.getConstant(0, MVT::i32),
|
|
ISD::SETLT);
|
|
|
|
// ilt r11, r1, 0
|
|
SDValue r11 = DAG.getSelectCC(DL,
|
|
r1, DAG.getConstant(0, OVT),
|
|
DAG.getConstant(-1, MVT::i32),
|
|
DAG.getConstant(0, MVT::i32),
|
|
ISD::SETLT);
|
|
|
|
// iadd r0, r0, r10
|
|
r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
|
|
|
|
// iadd r1, r1, r11
|
|
r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
|
|
|
|
// ixor r0, r0, r10
|
|
r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
|
|
|
|
// ixor r1, r1, r11
|
|
r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
|
|
|
|
// udiv r0, r0, r1
|
|
r0 = DAG.getNode(ISD::UDIV, DL, OVT, r0, r1);
|
|
|
|
// ixor r10, r10, r11
|
|
r10 = DAG.getNode(ISD::XOR, DL, OVT, r10, r11);
|
|
|
|
// iadd r0, r0, r10
|
|
r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
|
|
|
|
// ixor DST, r0, r10
|
|
SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
|
|
return DST;
|
|
}
|
|
|
|
SDValue
|
|
AMDGPUTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const {
|
|
return SDValue(Op.getNode(), 0);
|
|
}
|
|
|
|
SDValue
|
|
AMDGPUTargetLowering::LowerSREM8(SDValue Op, SelectionDAG &DAG) const {
|
|
SDLoc DL(Op);
|
|
EVT OVT = Op.getValueType();
|
|
MVT INTTY = MVT::i32;
|
|
if (OVT == MVT::v2i8) {
|
|
INTTY = MVT::v2i32;
|
|
} else if (OVT == MVT::v4i8) {
|
|
INTTY = MVT::v4i32;
|
|
}
|
|
SDValue LHS = DAG.getSExtOrTrunc(Op.getOperand(0), DL, INTTY);
|
|
SDValue RHS = DAG.getSExtOrTrunc(Op.getOperand(1), DL, INTTY);
|
|
LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
|
|
LHS = DAG.getSExtOrTrunc(LHS, DL, OVT);
|
|
return LHS;
|
|
}
|
|
|
|
SDValue
|
|
AMDGPUTargetLowering::LowerSREM16(SDValue Op, SelectionDAG &DAG) const {
|
|
SDLoc DL(Op);
|
|
EVT OVT = Op.getValueType();
|
|
MVT INTTY = MVT::i32;
|
|
if (OVT == MVT::v2i16) {
|
|
INTTY = MVT::v2i32;
|
|
} else if (OVT == MVT::v4i16) {
|
|
INTTY = MVT::v4i32;
|
|
}
|
|
SDValue LHS = DAG.getSExtOrTrunc(Op.getOperand(0), DL, INTTY);
|
|
SDValue RHS = DAG.getSExtOrTrunc(Op.getOperand(1), DL, INTTY);
|
|
LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
|
|
LHS = DAG.getSExtOrTrunc(LHS, DL, OVT);
|
|
return LHS;
|
|
}
|
|
|
|
SDValue
|
|
AMDGPUTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const {
|
|
SDLoc DL(Op);
|
|
EVT OVT = Op.getValueType();
|
|
SDValue LHS = Op.getOperand(0);
|
|
SDValue RHS = Op.getOperand(1);
|
|
// The LowerSREM32 function generates equivalent to the following IL.
|
|
// mov r0, LHS
|
|
// mov r1, RHS
|
|
// ilt r10, r0, 0
|
|
// ilt r11, r1, 0
|
|
// iadd r0, r0, r10
|
|
// iadd r1, r1, r11
|
|
// ixor r0, r0, r10
|
|
// ixor r1, r1, r11
|
|
// udiv r20, r0, r1
|
|
// umul r20, r20, r1
|
|
// sub r0, r0, r20
|
|
// iadd r0, r0, r10
|
|
// ixor DST, r0, r10
|
|
|
|
// mov r0, LHS
|
|
SDValue r0 = LHS;
|
|
|
|
// mov r1, RHS
|
|
SDValue r1 = RHS;
|
|
|
|
// ilt r10, r0, 0
|
|
SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT);
|
|
|
|
// ilt r11, r1, 0
|
|
SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT);
|
|
|
|
// iadd r0, r0, r10
|
|
r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
|
|
|
|
// iadd r1, r1, r11
|
|
r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
|
|
|
|
// ixor r0, r0, r10
|
|
r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
|
|
|
|
// ixor r1, r1, r11
|
|
r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
|
|
|
|
// udiv r20, r0, r1
|
|
SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1);
|
|
|
|
// umul r20, r20, r1
|
|
r20 = DAG.getNode(AMDGPUISD::UMUL, DL, OVT, r20, r1);
|
|
|
|
// sub r0, r0, r20
|
|
r0 = DAG.getNode(ISD::SUB, DL, OVT, r0, r20);
|
|
|
|
// iadd r0, r0, r10
|
|
r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
|
|
|
|
// ixor DST, r0, r10
|
|
SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
|
|
return DST;
|
|
}
|
|
|
|
SDValue
|
|
AMDGPUTargetLowering::LowerSREM64(SDValue Op, SelectionDAG &DAG) const {
|
|
return SDValue(Op.getNode(), 0);
|
|
}
|