forked from OSchip/llvm-project
19 lines
371 B
TableGen
19 lines
371 B
TableGen
// This tests to make sure we can parse tree patterns.
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// RUN: tblgen %s
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class TreeNode;
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class RegisterClass;
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def set : TreeNode;
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def plus : TreeNode;
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def imm : TreeNode;
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def R32 : RegisterClass;
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class Inst<dag T> {
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dag Pattern = T;
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}
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def ADDrr32 : Inst<(set R32, (plus R32, R32))>; // a = b + c
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def ADDri32 : Inst<(set R32, (plus R32, imm))>; // a = b + imm
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