forked from OSchip/llvm-project
46 lines
1.7 KiB
LLVM
46 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -addr-sink-using-gep=1 | FileCheck %s
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; Check that the CodeGenPrepare Pass
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; does not wrongly rewrite the address computed by Instruction %4
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; as [12 + Base:%this].
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; This test makes sure that:
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; - both the store and the first load instructions
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; within basic block labeled 'if.then' are not removed.
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; - the store instruction stores a value at address [60 + %this]
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; - the first load instruction loads a value at address [12 + %this]
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%class.A = type { %struct.B }
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%struct.B = type { %class.C, %class.D, %class.C, %class.D }
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%class.C = type { float, float, float }
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%class.D = type { [3 x %class.C] }
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define linkonce_odr void @foo(%class.A* nocapture %this, i32 %BoolValue) nounwind uwtable {
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entry:
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%cmp = icmp eq i32 %BoolValue, 0
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%address1 = getelementptr inbounds %class.A* %this, i64 0, i32 0, i32 3
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%address2 = getelementptr inbounds %class.A* %this, i64 0, i32 0, i32 1
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br i1 %cmp, label %if.else, label %if.then
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if.then: ; preds = %entry
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%0 = getelementptr inbounds %class.D* %address2, i64 0, i32 0, i64 0, i32 0
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%1 = load float* %0, align 4
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%2 = getelementptr inbounds float* %0, i64 3
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%3 = load float* %2, align 4
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%4 = getelementptr inbounds %class.D* %address1, i64 0, i32 0, i64 0, i32 0
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store float %1, float* %4, align 4
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br label %if.end
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if.else: ; preds = %entry
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br label %if.end
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if.end: ; preds = %if.then, %if.else, %entry
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ret void
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}
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; CHECK-LABEL: foo:
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; CHECK: movss 12([[THIS:%[a-zA-Z0-9]+]]), [[REGISTER:%[a-zA-Z0-9]+]]
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; CHECK-NEXT: movss [[REGISTER]], 60([[THIS]])
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