forked from OSchip/llvm-project
				
			
		
			
				
	
	
		
			100 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			YAML
		
	
	
	
			
		
		
	
	
			100 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			YAML
		
	
	
	
# RUN: llc -mtriple=aarch64--- -run-pass=machine-outliner \
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# RUN: -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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  define void @no-save1() #0 { ret void }
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  define void @no-save2() #0 { ret void }
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  define void @reg-save() #0 { ret void }
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  define void @stack-save() #0 { ret void }
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  attributes #0 = { minsize noinline noredzone "frame-pointer"="all" }  
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...
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---
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name:            no-save1
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tracksRegLiveness: true
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body:             |
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  bb.0:
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  liveins: $lr
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  $lr = ORRXri $xzr, 1
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  bb.1:
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    ; CHECK-LABEL: name:            no-save1
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    ; CHECK: BL [[FN:@OUTLINED_FUNCTION_[0-9]+]]
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    ; CHECK-NOT: STRXpre
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    ; CHECK-NOT: $lr =
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    ; CHECK-NOT: ORRXrs
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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  bb.2:
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    RET undef $lr  
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...
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---
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name:            no-save2
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tracksRegLiveness: true
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body:             |
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  bb.0:
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  liveins: $lr
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  $lr = ORRXri $xzr, 1
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  bb.1:
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    ; CHECK-LABEL: name:            no-save2
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    ; CHECK: BL [[FN]]
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    ; CHECK-NOT: STRXpre
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    ; CHECK-NOT: $lr =
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    ; CHECK-NOT: ORRXrs
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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  bb.2:
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    RET undef $lr  
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...
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---
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name:            reg-save
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tracksRegLiveness: true
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body:             |
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  bb.0:
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  liveins: $lr
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  $lr = ORRXri $xzr, 1
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  bb.1:
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  liveins: $lr
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    ; CHECK-LABEL: name:            reg-save
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    ; CHECK: $[[REG:x[0-9]+]] = ORRXrs $xzr, $lr, 0
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    ; CHECK-NEXT: BL [[FN]]
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    ; CHECK-NEXT: $lr = ORRXrs $xzr, $[[REG]], 0
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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  bb.2:
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  liveins: $lr
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    RET undef $lr  
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...
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---
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name:            stack-save
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tracksRegLiveness: true
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body:             |
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  bb.0:
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  liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
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  $lr = ORRXri $xzr, 1
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  bb.1:
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  liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
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    ; CHECK-LABEL: name:            stack-save
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    ; CHECK-NOT: BL
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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    $x12 = ADDXri $sp, 48, 0;
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  bb.2:
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  liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
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    RET undef $lr  
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