forked from OSchip/llvm-project
273 lines
9.0 KiB
LLVM
273 lines
9.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX7 %s
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; RUN: llc -global-isel -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s
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; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX900 %s
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; RUN: llc -global-isel -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX906 %s
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define amdgpu_ps i32 @scalar_xnor_i32_one_use(i32 inreg %a, i32 inreg %b) {
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; GCN-LABEL: scalar_xnor_i32_one_use:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_xnor_b32 s0, s0, s1
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%xor = xor i32 %a, %b
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%r0.val = xor i32 %xor, -1
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ret i32 %r0.val
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}
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; FIXME:
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; define amdgpu_ps i32 @scalar_xnor_v2i16_one_use(<2 x i16> inreg %a, <2 x i16> inreg %b) {
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; entry:
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; %xor = xor <2 x i16> %a, %b
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; %r0.val = xor <2 x i16> %xor, <i16 -1, i16 -1>
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; %cast = bitcast <2 x i16> %r0.val to i32
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; ret i32 %cast
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; }
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define amdgpu_ps <2 x i32> @scalar_xnor_i32_mul_use(i32 inreg %a, i32 inreg %b) {
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; GCN-LABEL: scalar_xnor_i32_mul_use:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_xor_b32 s1, s0, s1
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; GCN-NEXT: s_not_b32 s2, s1
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; GCN-NEXT: s_add_i32 s1, s1, s0
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; GCN-NEXT: s_mov_b32 s0, s2
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%xor = xor i32 %a, %b
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%r0.val = xor i32 %xor, -1
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%r1.val = add i32 %xor, %a
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%ins0 = insertelement <2 x i32> undef, i32 %r0.val, i32 0
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%ins1 = insertelement <2 x i32> %ins0, i32 %r1.val, i32 1
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ret <2 x i32> %ins1
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}
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define amdgpu_ps i64 @scalar_xnor_i64_one_use(i64 inreg %a, i64 inreg %b) {
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; GCN-LABEL: scalar_xnor_i64_one_use:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_xnor_b64 s[0:1], s[0:1], s[2:3]
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; GCN-NEXT: ; return to shader part epilog
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%xor = xor i64 %a, %b
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%r0.val = xor i64 %xor, -1
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ret i64 %r0.val
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}
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; FIXME:
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; define amdgpu_ps i64 @scalar_xnor_v4i16_one_use(<4 x i16> inreg %a, <4 x i16> inreg %b) {
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; %xor = xor <4 x i16> %a, %b
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; %ret = xor <4 x i16> %xor, <i16 -1, i16 -1, i16 -1, i16 -1>
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; %cast = bitcast <4 x i16> %ret to i64
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; ret i64 %cast
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; }
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define amdgpu_ps <2 x i64> @scalar_xnor_i64_mul_use(i64 inreg %a, i64 inreg %b) {
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; GCN-LABEL: scalar_xnor_i64_mul_use:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_mov_b32 s4, s0
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; GCN-NEXT: s_mov_b32 s5, s1
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; GCN-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3]
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; GCN-NEXT: s_not_b64 s[0:1], s[2:3]
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; GCN-NEXT: s_add_u32 s2, s2, s4
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; GCN-NEXT: s_cselect_b32 s4, 1, 0
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; GCN-NEXT: s_and_b32 s4, s4, 1
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; GCN-NEXT: s_cmp_lg_u32 s4, 0
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; GCN-NEXT: s_addc_u32 s3, s3, s5
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; GCN-NEXT: ; return to shader part epilog
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%xor = xor i64 %a, %b
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%r0.val = xor i64 %xor, -1
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%r1.val = add i64 %xor, %a
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%ins0 = insertelement <2 x i64> undef, i64 %r0.val, i32 0
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%ins1 = insertelement <2 x i64> %ins0, i64 %r1.val, i32 1
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ret <2 x i64> %ins1
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}
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define i32 @vector_xnor_i32_one_use(i32 %a, i32 %b) {
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; GCN-LABEL: vector_xnor_i32_one_use:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_xor_b32_e32 v0, v0, v1
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; GCN-NEXT: v_xor_b32_e32 v0, -1, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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entry:
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%xor = xor i32 %a, %b
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%r = xor i32 %xor, -1
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ret i32 %r
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}
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define i64 @vector_xnor_i64_one_use(i64 %a, i64 %b) {
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; GCN-LABEL: vector_xnor_i64_one_use:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_xor_b32_e32 v0, v0, v2
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; GCN-NEXT: v_xor_b32_e32 v1, v1, v3
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; GCN-NEXT: v_xor_b32_e32 v0, -1, v0
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; GCN-NEXT: v_xor_b32_e32 v1, -1, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
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entry:
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%xor = xor i64 %a, %b
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%r = xor i64 %xor, -1
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ret i64 %r
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}
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define amdgpu_ps float @xnor_s_v_i32_one_use(i32 inreg %s, i32 %v) {
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; GCN-LABEL: xnor_s_v_i32_one_use:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_xor_b32_e32 v0, s0, v0
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; GCN-NEXT: v_xor_b32_e32 v0, -1, v0
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; GCN-NEXT: ; return to shader part epilog
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%xor = xor i32 %s, %v
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%d = xor i32 %xor, -1
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%cast = bitcast i32 %d to float
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ret float %cast
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}
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define amdgpu_ps float @xnor_v_s_i32_one_use(i32 inreg %s, i32 %v) {
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; GCN-LABEL: xnor_v_s_i32_one_use:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_xor_b32_e32 v0, s0, v0
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; GCN-NEXT: v_xor_b32_e32 v0, -1, v0
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; GCN-NEXT: ; return to shader part epilog
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%xor = xor i32 %v, %s
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%d = xor i32 %xor, -1
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%cast = bitcast i32 %d to float
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ret float %cast
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}
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define amdgpu_ps <2 x float> @xnor_i64_s_v_one_use(i64 inreg %a, i64 %b64) {
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; GFX7-LABEL: xnor_i64_s_v_one_use:
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; GFX7: ; %bb.0: ; %entry
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; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 29
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; GFX7-NEXT: v_xor_b32_e32 v0, s0, v0
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; GFX7-NEXT: v_xor_b32_e32 v1, s1, v1
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; GFX7-NEXT: v_xor_b32_e32 v0, -1, v0
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; GFX7-NEXT: v_xor_b32_e32 v1, -1, v1
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; GFX7-NEXT: ; return to shader part epilog
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;
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; GFX8-LABEL: xnor_i64_s_v_one_use:
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; GFX8: ; %bb.0: ; %entry
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; GFX8-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]
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; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0
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; GFX8-NEXT: v_xor_b32_e32 v1, s1, v1
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; GFX8-NEXT: v_xor_b32_e32 v0, -1, v0
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; GFX8-NEXT: v_xor_b32_e32 v1, -1, v1
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; GFX8-NEXT: ; return to shader part epilog
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;
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; GFX900-LABEL: xnor_i64_s_v_one_use:
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; GFX900: ; %bb.0: ; %entry
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; GFX900-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]
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; GFX900-NEXT: v_xor_b32_e32 v0, s0, v0
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; GFX900-NEXT: v_xor_b32_e32 v1, s1, v1
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; GFX900-NEXT: v_xor_b32_e32 v0, -1, v0
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; GFX900-NEXT: v_xor_b32_e32 v1, -1, v1
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; GFX900-NEXT: ; return to shader part epilog
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;
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; GFX906-LABEL: xnor_i64_s_v_one_use:
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; GFX906: ; %bb.0: ; %entry
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; GFX906-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]
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; GFX906-NEXT: v_xor_b32_e32 v0, s0, v0
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; GFX906-NEXT: v_xor_b32_e32 v1, s1, v1
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; GFX906-NEXT: v_xor_b32_e32 v0, -1, v0
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; GFX906-NEXT: v_xor_b32_e32 v1, -1, v1
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; GFX906-NEXT: ; return to shader part epilog
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entry:
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%b = shl i64 %b64, 29
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%xor = xor i64 %a, %b
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%r0.val = xor i64 %xor, -1
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%cast = bitcast i64 %r0.val to <2 x float>
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ret <2 x float> %cast
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}
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define amdgpu_ps <2 x float> @xnor_i64_v_s_one_use(i64 inreg %a, i64 %b64) {
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; GFX7-LABEL: xnor_i64_v_s_one_use:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 29
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; GFX7-NEXT: v_xor_b32_e32 v0, s0, v0
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; GFX7-NEXT: v_xor_b32_e32 v1, s1, v1
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; GFX7-NEXT: v_xor_b32_e32 v0, -1, v0
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; GFX7-NEXT: v_xor_b32_e32 v1, -1, v1
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; GFX7-NEXT: ; return to shader part epilog
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;
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; GFX8-LABEL: xnor_i64_v_s_one_use:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]
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; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0
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; GFX8-NEXT: v_xor_b32_e32 v1, s1, v1
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; GFX8-NEXT: v_xor_b32_e32 v0, -1, v0
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; GFX8-NEXT: v_xor_b32_e32 v1, -1, v1
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; GFX8-NEXT: ; return to shader part epilog
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;
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; GFX900-LABEL: xnor_i64_v_s_one_use:
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; GFX900: ; %bb.0:
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; GFX900-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]
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; GFX900-NEXT: v_xor_b32_e32 v0, s0, v0
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; GFX900-NEXT: v_xor_b32_e32 v1, s1, v1
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; GFX900-NEXT: v_xor_b32_e32 v0, -1, v0
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; GFX900-NEXT: v_xor_b32_e32 v1, -1, v1
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; GFX900-NEXT: ; return to shader part epilog
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;
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; GFX906-LABEL: xnor_i64_v_s_one_use:
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; GFX906: ; %bb.0:
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; GFX906-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]
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; GFX906-NEXT: v_xor_b32_e32 v0, s0, v0
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; GFX906-NEXT: v_xor_b32_e32 v1, s1, v1
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; GFX906-NEXT: v_xor_b32_e32 v0, -1, v0
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; GFX906-NEXT: v_xor_b32_e32 v1, -1, v1
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; GFX906-NEXT: ; return to shader part epilog
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%b = shl i64 %b64, 29
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%xor = xor i64 %b, %a
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%r0.val = xor i64 %xor, -1
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%cast = bitcast i64 %r0.val to <2 x float>
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ret <2 x float> %cast
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}
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define i32 @vector_xor_na_b_i32_one_use(i32 %a, i32 %b) {
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; GCN-LABEL: vector_xor_na_b_i32_one_use:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_xor_b32_e32 v0, -1, v0
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; GCN-NEXT: v_xor_b32_e32 v0, v0, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
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entry:
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%na = xor i32 %a, -1
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%r = xor i32 %na, %b
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ret i32 %r
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}
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define i32 @vector_xor_a_nb_i32_one_use(i32 %a, i32 %b) {
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; GCN-LABEL: vector_xor_a_nb_i32_one_use:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_xor_b32_e32 v1, -1, v1
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; GCN-NEXT: v_xor_b32_e32 v0, v0, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
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entry:
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%nb = xor i32 %b, -1
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%r = xor i32 %a, %nb
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ret i32 %r
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}
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define amdgpu_ps <2 x i32> @scalar_xor_a_nb_i64_one_use(i64 inreg %a, i64 inreg %b) {
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; GCN-LABEL: scalar_xor_a_nb_i64_one_use:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_not_b64 s[2:3], s[2:3]
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; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%nb = xor i64 %b, -1
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%r0.val = xor i64 %a, %nb
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%cast = bitcast i64 %r0.val to <2 x i32>
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ret <2 x i32> %cast
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}
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define amdgpu_ps <2 x i32> @scalar_xor_na_b_i64_one_use(i64 inreg %a, i64 inreg %b) {
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; GCN-LABEL: scalar_xor_na_b_i64_one_use:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_not_b64 s[0:1], s[0:1]
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; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%na = xor i64 %a, -1
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%r0.val = xor i64 %na, %b
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%cast = bitcast i64 %r0.val to <2 x i32>
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ret <2 x i32> %cast
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}
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