forked from OSchip/llvm-project
249 lines
10 KiB
YAML
249 lines
10 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=x86-64 -mattr=+x87 -mattr=-sse -run-pass none -o - %s | FileCheck %s
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# This test ensures that the MIR parser parses the x87 fpsw and fpcw regs
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--- |
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declare float @llvm.sqrt.f32(float)
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define void @f1(float* %a, float* %b) {
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%1 = load float, float* %a, align 4
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%2 = load float, float* %b, align 4
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%sub = fsub float %1, %2
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store float %sub, float* %a, align 4
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ret void
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}
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define void @f2(double* %a, double* %b) {
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%1 = load double, double* %a, align 8
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%2 = load double, double* %b, align 8
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%add = fadd double %1, %2
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store double %add, double* %a, align 8
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ret void
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}
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define void @f3(x86_fp80* %a, x86_fp80* %b) {
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%1 = load x86_fp80, x86_fp80* %a, align 16
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%2 = load x86_fp80, x86_fp80* %b, align 16
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%mul = fmul x86_fp80 %1, %2
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store x86_fp80 %mul, x86_fp80* %a, align 16
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ret void
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}
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define void @f4(float* %a, float* %b) {
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%1 = load float, float* %a, align 4
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%2 = load float, float* %b, align 4
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%div = fdiv float %1, %2
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store float %div, float* %a, align 4
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ret void
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}
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define void @f5(float* %val, double* %ret) {
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%1 = load float, float* %val, align 4
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%res = fpext float %1 to double
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store double %res, double* %ret, align 8
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ret void
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}
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define void @f6(double* %val, float* %ret) {
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%1 = load double, double* %val, align 8
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%res = fptrunc double %1 to float
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store float %res, float* %ret, align 4
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ret void
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}
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define void @f7(float* %a) {
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%1 = load float, float* %a, align 4
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%res = call float @llvm.sqrt.f32(float %1)
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store float %res, float* %a, align 4
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ret void
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}
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...
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---
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name: f1
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alignment: 16
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tracksRegLiveness: true
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liveins:
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- { reg: '$rdi' }
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- { reg: '$rsi' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.0):
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liveins: $rdi, $rsi
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; CHECK-LABEL: name: f1
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; CHECK: liveins: $rdi, $rsi
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; CHECK: renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
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; CHECK: renamable $fp0 = SUB_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)
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; CHECK: ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
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; CHECK: RET 0
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renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
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renamable $fp0 = SUB_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)
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ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
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RET 0
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...
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---
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name: f2
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alignment: 16
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tracksRegLiveness: true
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liveins:
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- { reg: '$rdi' }
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- { reg: '$rsi' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.0):
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liveins: $rdi, $rsi
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; CHECK-LABEL: name: f2
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; CHECK: liveins: $rdi, $rsi
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; CHECK: renamable $fp0 = LD_Fp64m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.a)
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; CHECK: renamable $fp0 = ADD_Fp64m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.b)
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; CHECK: ST_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.a)
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; CHECK: RET 0
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renamable $fp0 = LD_Fp64m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.a)
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renamable $fp0 = ADD_Fp64m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.b)
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ST_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.a)
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RET 0
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...
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---
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name: f3
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alignment: 16
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tracksRegLiveness: true
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liveins:
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- { reg: '$rdi' }
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- { reg: '$rsi' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.0):
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liveins: $rdi, $rsi
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; CHECK-LABEL: name: f3
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; CHECK: liveins: $rdi, $rsi
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; CHECK: renamable $fp0 = LD_Fp80m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.a, align 16)
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; CHECK: renamable $fp1 = LD_Fp80m killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.b, align 16)
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; CHECK: renamable $fp0 = MUL_Fp80 killed renamable $fp0, killed renamable $fp1, implicit-def dead $fpsw, implicit $fpcw
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; CHECK: ST_FpP80m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 10 into %ir.a, align 16)
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; CHECK: RET 0
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renamable $fp0 = LD_Fp80m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.a, align 16)
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renamable $fp1 = LD_Fp80m killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.b, align 16)
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renamable $fp0 = MUL_Fp80 killed renamable $fp0, killed renamable $fp1, implicit-def dead $fpsw, implicit $fpcw
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ST_FpP80m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 10 into %ir.a, align 16)
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RET 0
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...
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---
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name: f4
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alignment: 16
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tracksRegLiveness: true
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liveins:
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- { reg: '$rdi' }
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- { reg: '$rsi' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.0):
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liveins: $rdi, $rsi
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; CHECK-LABEL: name: f4
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; CHECK: liveins: $rdi, $rsi
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; CHECK: renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
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; CHECK: renamable $fp0 = DIV_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)
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; CHECK: ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
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; CHECK: RET 0
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renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
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renamable $fp0 = DIV_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)
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ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
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RET 0
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...
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---
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name: f5
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alignment: 16
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tracksRegLiveness: true
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liveins:
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- { reg: '$rdi' }
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- { reg: '$rsi' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.0):
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liveins: $rdi, $rsi
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; CHECK-LABEL: name: f5
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; CHECK: liveins: $rdi, $rsi
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; CHECK: renamable $fp0 = LD_Fp32m64 killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.val)
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; CHECK: ST_Fp64m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.ret)
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; CHECK: RET 0
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renamable $fp0 = LD_Fp32m64 killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.val)
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ST_Fp64m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.ret)
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RET 0
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...
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---
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name: f6
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alignment: 16
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tracksRegLiveness: true
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liveins:
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- { reg: '$rdi' }
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- { reg: '$rsi' }
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frameInfo:
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maxAlignment: 4
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stack:
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- { id: 0, size: 4, alignment: 4 }
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.0):
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liveins: $rdi, $rsi
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; CHECK-LABEL: name: f6
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; CHECK: liveins: $rdi, $rsi
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; CHECK: renamable $fp0 = LD_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.val)
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; CHECK: ST_Fp64m32 %stack.0, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %stack.0)
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; CHECK: renamable $fp0 = LD_Fp32m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %stack.0)
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; CHECK: ST_Fp32m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.ret)
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; CHECK: RET 0
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renamable $fp0 = LD_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.val)
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ST_Fp64m32 %stack.0, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %stack.0)
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renamable $fp0 = LD_Fp32m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %stack.0)
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ST_Fp32m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.ret)
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RET 0
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...
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---
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name: f7
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alignment: 16
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tracksRegLiveness: true
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liveins:
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- { reg: '$rdi' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.0):
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liveins: $rdi
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; CHECK-LABEL: name: f7
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; CHECK: liveins: $rdi
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; CHECK: renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
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; CHECK: renamable $fp0 = SQRT_Fp32 killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw
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; CHECK: ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
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; CHECK: RET 0
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renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
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renamable $fp0 = SQRT_Fp32 killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw
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ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
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RET 0
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...
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