forked from OSchip/llvm-project
116 lines
2.9 KiB
ArmAsm
116 lines
2.9 KiB
ArmAsm
# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+e -show-encoding \
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# RUN: | FileCheck -check-prefix=CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+e < %s \
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# RUN: | llvm-objdump -M no-aliases -d -r - \
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# RUN: | FileCheck -check-prefix=CHECK-ASM-AND-OBJ %s
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# This file provides a basic sanity check for RV32E, checking that the expected
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# set of registers and instructions are accepted.
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# CHECK-ASM-AND-OBJ: lui zero, 1
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lui x0, 1
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# CHECK-ASM-AND-OBJ: auipc ra, 2
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auipc x1, 2
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# CHECK-ASM-AND-OBJ: jal sp, 4
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jal x2, 4
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# CHECK-ASM-AND-OBJ: jalr gp, 4(gp)
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jalr x3, x3, 4
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# CHECK-ASM-AND-OBJ: beq tp, t0, 8
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beq x4, x5, 8
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# CHECK-ASM-AND-OBJ: bne t1, t2, 12
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bne x6, x7, 12
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# CHECK-ASM-AND-OBJ: blt s0, s1, 16
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blt x8, x9, 16
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# CHECK-ASM-AND-OBJ: bge a0, a1, 20
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bge x10, x11, 20
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# CHECK-ASM-AND-OBJ: bgeu a2, a3, 24
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bgeu x12, x13, 24
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# CHECK-ASM-AND-OBJ: lb a4, 25(a5)
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lb x14, 25(x15)
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# CHECK-ASM-AND-OBJ: lh zero, 26(ra)
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lh zero, 26(ra)
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# CHECK-ASM-AND-OBJ: lw sp, 28(gp)
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lw sp, 28(gp)
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# CHECK-ASM-AND-OBJ: lbu tp, 29(t0)
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lbu tp, 29(t0)
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# CHECK-ASM-AND-OBJ: lhu t1, 30(t2)
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lhu t1, 30(t2)
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# CHECK-ASM-AND-OBJ: sb s0, 31(s1)
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sb s0, 31(s1)
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# CHECK-ASM-AND-OBJ: sh a0, 32(a1)
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sh a0, 32(a1)
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# CHECK-ASM-AND-OBJ: sw a2, 36(a3)
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sw a2, 36(a3)
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# CHECK-ASM-AND-OBJ: addi a4, a5, 37
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addi a4, a5, 37
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# CHECK-ASM-AND-OBJ: slti a0, a2, -20
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slti a0, a2, -20
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# CHECK-ASM-AND-OBJ: xori tp, t1, -99
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xori tp, t1, -99
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# CHECK-ASM-AND-OBJ: ori a0, a1, -2048
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ori a0, a1, -2048
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# CHECK-ASM-AND-OBJ: andi ra, sp, 2047
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andi ra, sp, 2047
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# CHECK-ASM-AND-OBJ: slli t1, t1, 31
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slli t1, t1, 31
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# CHECK-ASM-AND-OBJ: srli a0, a4, 0
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srli a0, a4, 0
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# CHECK-ASM-AND-OBJ: srai a1, sp, 15
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srai a1, sp, 15
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# CHECK-ASM-AND-OBJ: slli t0, t1, 13
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slli t0, t1, 13
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# CHECK-ASM-AND-OBJ: add ra, zero, zero
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add ra, zero, zero
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# CHECK-ASM-AND-OBJ: sub t0, t2, t1
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sub t0, t2, t1
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# CHECK-ASM-AND-OBJ: sll a5, a4, a3
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sll a5, a4, a3
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# CHECK-ASM-AND-OBJ: slt s0, s0, s0
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slt s0, s0, s0
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# CHECK-ASM-AND-OBJ: sltu gp, a0, a1
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sltu gp, a0, a1
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# CHECK-ASM-AND-OBJ: xor s1, s0, s1
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xor s1, s0, s1
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# CHECK-ASM-AND-OBJ: srl a0, s0, t0
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srl a0, s0, t0
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# CHECK-ASM-AND-OBJ: sra t0, a3, zero
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sra t0, a3, zero
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# CHECK-ASM-AND-OBJ: or a5, t1, ra
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or a5, t1, ra
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# CHECK-ASM-AND-OBJ: and a0, s1, a3
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and a0, s1, a3
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# CHECK-ASM-AND-OBJ: fence iorw, iorw
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fence iorw, iorw
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# CHECK-ASM-AND-OBJ: fence.tso
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fence.tso
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# CHECK-ASM-AND-OBJ: fence.i
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fence.i
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# CHECK-ASM-AND-OBJ: ecall
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ecall
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# CHECK-ASM-AND-OBJ: ebreak
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ebreak
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# CHECK-ASM-AND-OBJ: unimp
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unimp
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# CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1
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csrrw t0, 0xfff, t1
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# CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero
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csrrs s0, 0xc00, x0
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# CHECK-ASM-AND-OBJ: csrrs s0, fflags, a5
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csrrs s0, 0x001, a5
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# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra
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csrrc sp, 0x000, ra
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# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0
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csrrwi a5, 0x000, 0
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# CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31
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csrrsi t2, 0xfff, 31
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# CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5
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csrrci t1, 0x140, 5
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