forked from OSchip/llvm-project
42 lines
1.6 KiB
ArmAsm
42 lines
1.6 KiB
ArmAsm
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -instruction-tables < %s | FileCheck %s
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rdrand %ax
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rdrand %eax
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rdrand %rax
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 17 1 5.33 U rdrandw %ax
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# CHECK-NEXT: 17 1 5.33 U rdrandl %eax
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# CHECK-NEXT: 17 1 5.33 U rdrandq %rax
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# CHECK: Resources:
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# CHECK-NEXT: [0] - HWDivider
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# CHECK-NEXT: [1] - HWFPDivider
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# CHECK-NEXT: [2] - HWPort0
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# CHECK-NEXT: [3] - HWPort1
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# CHECK-NEXT: [4] - HWPort2
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# CHECK-NEXT: [5] - HWPort3
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# CHECK-NEXT: [6] - HWPort4
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# CHECK-NEXT: [7] - HWPort5
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# CHECK-NEXT: [8] - HWPort6
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# CHECK-NEXT: [9] - HWPort7
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
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# CHECK-NEXT: - - 16.00 16.00 1.50 1.50 - 16.00 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
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# CHECK-NEXT: - - 5.33 5.33 0.50 0.50 - 5.33 - - rdrandw %ax
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# CHECK-NEXT: - - 5.33 5.33 0.50 0.50 - 5.33 - - rdrandl %eax
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# CHECK-NEXT: - - 5.33 5.33 0.50 0.50 - 5.33 - - rdrandq %rax
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