forked from OSchip/llvm-project
1340 lines
47 KiB
C++
1340 lines
47 KiB
C++
//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ARMMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mccodeemitter"
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#include "MCTargetDesc/ARMAddressingModes.h"
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#include "MCTargetDesc/ARMBaseInfo.h"
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#include "MCTargetDesc/ARMFixupKinds.h"
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#include "MCTargetDesc/ARMMCExpr.h"
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#include "MCTargetDesc/ARMMCTargetDesc.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
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STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
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namespace {
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class ARMMCCodeEmitter : public MCCodeEmitter {
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ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
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void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
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const MCInstrInfo &MCII;
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const MCSubtargetInfo &STI;
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public:
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ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
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MCContext &ctx)
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: MCII(mcii), STI(sti) {
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}
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~ARMMCCodeEmitter() {}
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bool isThumb() const {
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// FIXME: Can tablegen auto-generate this?
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return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
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}
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bool isThumb2() const {
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return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
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}
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bool isTargetDarwin() const {
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Triple TT(STI.getTargetTriple());
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Triple::OSType OS = TT.getOS();
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return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
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}
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unsigned getMachineSoImmOpValue(unsigned SoImm) const;
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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unsigned getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
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/// the specified operand. This is used for operands with :lower16: and
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/// :upper16: prefixes.
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uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
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unsigned &Reg, unsigned &Imm,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
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/// BL branch target.
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uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
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/// BLX branch target.
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uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
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uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
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uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
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uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getBranchTargetOpValue - Return encoding info for 24-bit immediate
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/// branch target.
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uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
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/// immediate Thumb2 direct branch target.
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uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
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/// branch target.
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uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAdrLabelOpValue - Return encoding info for 12-bit immediate
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/// ADR label target.
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uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
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/// operand.
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uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
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uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups)const;
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/// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
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/// operand.
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uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
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/// operand as needed by load/store instructions.
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uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getLdStmModeOpValue - Return encoding for load/store multiple mode.
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uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
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switch (Mode) {
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default: assert(0 && "Unknown addressing sub-mode!");
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case ARM_AM::da: return 0;
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case ARM_AM::ia: return 1;
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case ARM_AM::db: return 2;
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case ARM_AM::ib: return 3;
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}
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}
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/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
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///
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unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
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switch (ShOpc) {
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default: llvm_unreachable("Unknown shift opc!");
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case ARM_AM::no_shift:
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case ARM_AM::lsl: return 0;
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case ARM_AM::lsr: return 1;
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case ARM_AM::asr: return 2;
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case ARM_AM::ror:
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case ARM_AM::rrx: return 3;
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}
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return 0;
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}
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/// getAddrMode2OpValue - Return encoding for addrmode2 operands.
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uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
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uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
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uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAddrMode3OpValue - Return encoding for addrmode3 operands.
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uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
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/// operand.
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uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
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uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
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uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
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uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getCCOutOpValue - Return encoding of the 's' bit.
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unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
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// '1' respectively.
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return MI.getOperand(Op).getReg() == ARM::CPSR;
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}
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/// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
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unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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unsigned SoImm = MI.getOperand(Op).getImm();
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int SoImmVal = ARM_AM::getSOImmVal(SoImm);
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assert(SoImmVal != -1 && "Not a valid so_imm value!");
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// Encode rotate_imm.
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unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
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<< ARMII::SoRotImmShift;
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// Encode immed_8.
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Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
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return Binary;
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}
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/// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
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unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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unsigned SoImm = MI.getOperand(Op).getImm();
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unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
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assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
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return Encoded;
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}
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unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getSORegOpValue - Return an encoded so_reg shifted register value.
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unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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switch (MI.getOperand(Op).getImm()) {
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default: assert (0 && "Not a valid rot_imm value!");
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case 0: return 0;
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case 8: return 1;
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case 16: return 2;
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case 24: return 3;
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}
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}
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unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return MI.getOperand(Op).getImm() - 1;
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}
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unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return 64 - MI.getOperand(Op).getImm();
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}
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unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getMsbOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
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unsigned EncodedValue) const;
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unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
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unsigned EncodedValue) const;
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unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
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unsigned EncodedValue) const;
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unsigned VFPThumb2PostEncoder(const MCInst &MI,
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unsigned EncodedValue) const;
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void EmitByte(unsigned char C, raw_ostream &OS) const {
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OS << (char)C;
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}
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void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
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// Output the constant in little endian byte order.
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for (unsigned i = 0; i != Size; ++i) {
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EmitByte(Val & 255, OS);
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Val >>= 8;
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}
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}
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new ARMMCCodeEmitter(MCII, STI, Ctx);
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}
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/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
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/// instructions, and rewrite them to their Thumb2 form if we are currently in
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/// Thumb2 mode.
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unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
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unsigned EncodedValue) const {
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if (isThumb2()) {
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// NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
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// to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
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// set to 1111.
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unsigned Bit24 = EncodedValue & 0x01000000;
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unsigned Bit28 = Bit24 << 4;
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EncodedValue &= 0xEFFFFFFF;
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EncodedValue |= Bit28;
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EncodedValue |= 0x0F000000;
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}
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return EncodedValue;
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}
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/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
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/// instructions, and rewrite them to their Thumb2 form if we are currently in
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/// Thumb2 mode.
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unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
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unsigned EncodedValue) const {
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if (isThumb2()) {
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EncodedValue &= 0xF0FFFFFF;
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EncodedValue |= 0x09000000;
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}
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return EncodedValue;
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}
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/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
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/// instructions, and rewrite them to their Thumb2 form if we are currently in
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/// Thumb2 mode.
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unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
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unsigned EncodedValue) const {
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if (isThumb2()) {
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EncodedValue &= 0x00FFFFFF;
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EncodedValue |= 0xEE000000;
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}
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return EncodedValue;
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}
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/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
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/// them to their Thumb2 form if we are currently in Thumb2 mode.
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unsigned ARMMCCodeEmitter::
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VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
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if (isThumb2()) {
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EncodedValue &= 0x0FFFFFFF;
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EncodedValue |= 0xE0000000;
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}
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return EncodedValue;
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}
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned ARMMCCodeEmitter::
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getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (MO.isReg()) {
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unsigned Reg = MO.getReg();
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unsigned RegNo = getARMRegisterNumbering(Reg);
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// Q registers are encoded as 2x their register number.
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switch (Reg) {
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default:
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return RegNo;
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case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
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case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
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case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
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case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
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return 2 * RegNo;
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}
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} else if (MO.isImm()) {
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return static_cast<unsigned>(MO.getImm());
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} else if (MO.isFPImm()) {
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return static_cast<unsigned>(APFloat(MO.getFPImm())
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.bitcastToAPInt().getHiBits(32).getLimitedValue());
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}
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llvm_unreachable("Unable to encode MCOperand!");
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return 0;
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}
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/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
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bool ARMMCCodeEmitter::
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EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
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unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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|
const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
|
|
|
|
Reg = getARMRegisterNumbering(MO.getReg());
|
|
|
|
int32_t SImm = MO1.getImm();
|
|
bool isAdd = true;
|
|
|
|
// Special value for #-0
|
|
if (SImm == INT32_MIN)
|
|
SImm = 0;
|
|
|
|
// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
|
|
if (SImm < 0) {
|
|
SImm = -SImm;
|
|
isAdd = false;
|
|
}
|
|
|
|
Imm = SImm;
|
|
return isAdd;
|
|
}
|
|
|
|
/// getBranchTargetOpValue - Helper function to get the branch target operand,
|
|
/// which is either an immediate or requires a fixup.
|
|
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
|
|
unsigned FixupKind,
|
|
SmallVectorImpl<MCFixup> &Fixups) {
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
|
|
// If the destination is an immediate, we have nothing to do.
|
|
if (MO.isImm()) return MO.getImm();
|
|
assert(MO.isExpr() && "Unexpected branch target type!");
|
|
const MCExpr *Expr = MO.getExpr();
|
|
MCFixupKind Kind = MCFixupKind(FixupKind);
|
|
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
|
|
|
|
// All of the information is in the fixup.
|
|
return 0;
|
|
}
|
|
|
|
/// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups);
|
|
}
|
|
|
|
/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
|
|
/// BLX branch target.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups);
|
|
}
|
|
|
|
/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups);
|
|
}
|
|
|
|
/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups);
|
|
}
|
|
|
|
/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
|
|
}
|
|
|
|
/// Return true if this branch has a non-always predication
|
|
static bool HasConditionalBranch(const MCInst &MI) {
|
|
int NumOp = MI.getNumOperands();
|
|
if (NumOp >= 2) {
|
|
for (int i = 0; i < NumOp-1; ++i) {
|
|
const MCOperand &MCOp1 = MI.getOperand(i);
|
|
const MCOperand &MCOp2 = MI.getOperand(i + 1);
|
|
if (MCOp1.isImm() && MCOp2.isReg() &&
|
|
(MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
|
|
if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
|
|
/// target.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// FIXME: This really, really shouldn't use TargetMachine. We don't want
|
|
// coupling between MC and TM anywhere we can help it.
|
|
if (isThumb2())
|
|
return
|
|
::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
|
|
return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
|
|
}
|
|
|
|
/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
|
|
/// target.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
if (HasConditionalBranch(MI))
|
|
return ::getBranchTargetOpValue(MI, OpIdx,
|
|
ARM::fixup_arm_condbranch, Fixups);
|
|
return ::getBranchTargetOpValue(MI, OpIdx,
|
|
ARM::fixup_arm_uncondbranch, Fixups);
|
|
}
|
|
|
|
|
|
|
|
|
|
/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
|
|
/// immediate branch target.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
unsigned Val =
|
|
::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
|
|
bool I = (Val & 0x800000);
|
|
bool J1 = (Val & 0x400000);
|
|
bool J2 = (Val & 0x200000);
|
|
if (I ^ J1)
|
|
Val &= ~0x400000;
|
|
else
|
|
Val |= 0x400000;
|
|
|
|
if (I ^ J2)
|
|
Val &= ~0x200000;
|
|
else
|
|
Val |= 0x200000;
|
|
|
|
return Val;
|
|
}
|
|
|
|
/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
|
|
/// target.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
|
|
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
|
|
Fixups);
|
|
}
|
|
|
|
/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
|
|
/// target.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
|
|
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
|
|
Fixups);
|
|
}
|
|
|
|
/// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
|
|
/// target.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
|
|
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
|
|
Fixups);
|
|
}
|
|
|
|
/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
|
|
/// operand.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &) const {
|
|
// [Rn, Rm]
|
|
// {5-3} = Rm
|
|
// {2-0} = Rn
|
|
const MCOperand &MO1 = MI.getOperand(OpIdx);
|
|
const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
|
|
unsigned Rn = getARMRegisterNumbering(MO1.getReg());
|
|
unsigned Rm = getARMRegisterNumbering(MO2.getReg());
|
|
return (Rm << 3) | Rn;
|
|
}
|
|
|
|
/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// {17-13} = reg
|
|
// {12} = (U)nsigned (add == '1', sub == '0')
|
|
// {11-0} = imm12
|
|
unsigned Reg, Imm12;
|
|
bool isAdd = true;
|
|
// If The first operand isn't a register, we have a label reference.
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
if (!MO.isReg()) {
|
|
Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
|
|
Imm12 = 0;
|
|
isAdd = false ; // 'U' bit is set as part of the fixup.
|
|
|
|
assert(MO.isExpr() && "Unexpected machine operand type!");
|
|
const MCExpr *Expr = MO.getExpr();
|
|
|
|
MCFixupKind Kind;
|
|
if (isThumb2())
|
|
Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
|
|
else
|
|
Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
|
|
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
|
|
|
|
++MCNumCPRelocations;
|
|
} else
|
|
isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
|
|
|
|
uint32_t Binary = Imm12 & 0xfff;
|
|
// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
|
|
if (isAdd)
|
|
Binary |= (1 << 12);
|
|
Binary |= (Reg << 13);
|
|
return Binary;
|
|
}
|
|
|
|
/// getT2AddrModeImm8s4OpValue - Return encoding info for
|
|
/// 'reg +/- imm8<<2' operand.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// {12-9} = reg
|
|
// {8} = (U)nsigned (add == '1', sub == '0')
|
|
// {7-0} = imm8
|
|
unsigned Reg, Imm8;
|
|
bool isAdd = true;
|
|
// If The first operand isn't a register, we have a label reference.
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
if (!MO.isReg()) {
|
|
Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
|
|
Imm8 = 0;
|
|
isAdd = false ; // 'U' bit is set as part of the fixup.
|
|
|
|
assert(MO.isExpr() && "Unexpected machine operand type!");
|
|
const MCExpr *Expr = MO.getExpr();
|
|
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
|
|
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
|
|
|
|
++MCNumCPRelocations;
|
|
} else
|
|
isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
|
|
|
|
uint32_t Binary = (Imm8 >> 2) & 0xff;
|
|
// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
|
|
if (isAdd)
|
|
Binary |= (1 << 8);
|
|
Binary |= (Reg << 9);
|
|
return Binary;
|
|
}
|
|
|
|
// FIXME: This routine assumes that a binary
|
|
// expression will always result in a PCRel expression
|
|
// In reality, its only true if one or more subexpressions
|
|
// is itself a PCRel (i.e. "." in asm or some other pcrel construct)
|
|
// but this is good enough for now.
|
|
static bool EvaluateAsPCRel(const MCExpr *Expr) {
|
|
switch (Expr->getKind()) {
|
|
default: assert(0 && "Unexpected expression type");
|
|
case MCExpr::SymbolRef: return false;
|
|
case MCExpr::Binary: return true;
|
|
}
|
|
}
|
|
|
|
uint32_t
|
|
ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// {20-16} = imm{15-12}
|
|
// {11-0} = imm{11-0}
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
if (MO.isImm())
|
|
// Hi / lo 16 bits already extracted during earlier passes.
|
|
return static_cast<unsigned>(MO.getImm());
|
|
|
|
// Handle :upper16: and :lower16: assembly prefixes.
|
|
const MCExpr *E = MO.getExpr();
|
|
if (E->getKind() == MCExpr::Target) {
|
|
const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
|
|
E = ARM16Expr->getSubExpr();
|
|
|
|
MCFixupKind Kind;
|
|
switch (ARM16Expr->getKind()) {
|
|
default: assert(0 && "Unsupported ARMFixup");
|
|
case ARMMCExpr::VK_ARM_HI16:
|
|
if (!isTargetDarwin() && EvaluateAsPCRel(E))
|
|
Kind = MCFixupKind(isThumb2()
|
|
? ARM::fixup_t2_movt_hi16_pcrel
|
|
: ARM::fixup_arm_movt_hi16_pcrel);
|
|
else
|
|
Kind = MCFixupKind(isThumb2()
|
|
? ARM::fixup_t2_movt_hi16
|
|
: ARM::fixup_arm_movt_hi16);
|
|
break;
|
|
case ARMMCExpr::VK_ARM_LO16:
|
|
if (!isTargetDarwin() && EvaluateAsPCRel(E))
|
|
Kind = MCFixupKind(isThumb2()
|
|
? ARM::fixup_t2_movw_lo16_pcrel
|
|
: ARM::fixup_arm_movw_lo16_pcrel);
|
|
else
|
|
Kind = MCFixupKind(isThumb2()
|
|
? ARM::fixup_t2_movw_lo16
|
|
: ARM::fixup_arm_movw_lo16);
|
|
break;
|
|
}
|
|
Fixups.push_back(MCFixup::Create(0, E, Kind));
|
|
return 0;
|
|
};
|
|
|
|
llvm_unreachable("Unsupported MCExpr type in MCOperand!");
|
|
return 0;
|
|
}
|
|
|
|
uint32_t ARMMCCodeEmitter::
|
|
getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
const MCOperand &MO1 = MI.getOperand(OpIdx+1);
|
|
const MCOperand &MO2 = MI.getOperand(OpIdx+2);
|
|
unsigned Rn = getARMRegisterNumbering(MO.getReg());
|
|
unsigned Rm = getARMRegisterNumbering(MO1.getReg());
|
|
unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
|
|
bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
|
|
ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
|
|
unsigned SBits = getShiftOp(ShOp);
|
|
|
|
// {16-13} = Rn
|
|
// {12} = isAdd
|
|
// {11-0} = shifter
|
|
// {3-0} = Rm
|
|
// {4} = 0
|
|
// {6-5} = type
|
|
// {11-7} = imm
|
|
uint32_t Binary = Rm;
|
|
Binary |= Rn << 13;
|
|
Binary |= SBits << 5;
|
|
Binary |= ShImm << 7;
|
|
if (isAdd)
|
|
Binary |= 1 << 12;
|
|
return Binary;
|
|
}
|
|
|
|
uint32_t ARMMCCodeEmitter::
|
|
getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// {17-14} Rn
|
|
// {13} 1 == imm12, 0 == Rm
|
|
// {12} isAdd
|
|
// {11-0} imm12/Rm
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
unsigned Rn = getARMRegisterNumbering(MO.getReg());
|
|
uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
|
|
Binary |= Rn << 14;
|
|
return Binary;
|
|
}
|
|
|
|
uint32_t ARMMCCodeEmitter::
|
|
getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// {13} 1 == imm12, 0 == Rm
|
|
// {12} isAdd
|
|
// {11-0} imm12/Rm
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
const MCOperand &MO1 = MI.getOperand(OpIdx+1);
|
|
unsigned Imm = MO1.getImm();
|
|
bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
|
|
bool isReg = MO.getReg() != 0;
|
|
uint32_t Binary = ARM_AM::getAM2Offset(Imm);
|
|
// if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
|
|
if (isReg) {
|
|
ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
|
|
Binary <<= 7; // Shift amount is bits [11:7]
|
|
Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
|
|
Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
|
|
}
|
|
return Binary | (isAdd << 12) | (isReg << 13);
|
|
}
|
|
|
|
uint32_t ARMMCCodeEmitter::
|
|
getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// {9} 1 == imm8, 0 == Rm
|
|
// {8} isAdd
|
|
// {7-4} imm7_4/zero
|
|
// {3-0} imm3_0/Rm
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
const MCOperand &MO1 = MI.getOperand(OpIdx+1);
|
|
unsigned Imm = MO1.getImm();
|
|
bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
|
|
bool isImm = MO.getReg() == 0;
|
|
uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
|
|
// if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
|
|
if (!isImm)
|
|
Imm8 = getARMRegisterNumbering(MO.getReg());
|
|
return Imm8 | (isAdd << 8) | (isImm << 9);
|
|
}
|
|
|
|
uint32_t ARMMCCodeEmitter::
|
|
getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// {13} 1 == imm8, 0 == Rm
|
|
// {12-9} Rn
|
|
// {8} isAdd
|
|
// {7-4} imm7_4/zero
|
|
// {3-0} imm3_0/Rm
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
const MCOperand &MO1 = MI.getOperand(OpIdx+1);
|
|
const MCOperand &MO2 = MI.getOperand(OpIdx+2);
|
|
unsigned Rn = getARMRegisterNumbering(MO.getReg());
|
|
unsigned Imm = MO2.getImm();
|
|
bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
|
|
bool isImm = MO1.getReg() == 0;
|
|
uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
|
|
// if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
|
|
if (!isImm)
|
|
Imm8 = getARMRegisterNumbering(MO1.getReg());
|
|
return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
|
|
}
|
|
|
|
/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// [SP, #imm]
|
|
// {7-0} = imm8
|
|
const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
|
|
assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
|
|
"Unexpected base register!");
|
|
|
|
// The immediate is already shifted for the implicit zeroes, so no change
|
|
// here.
|
|
return MO1.getImm() & 0xff;
|
|
}
|
|
|
|
/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// [Rn, #imm]
|
|
// {7-3} = imm5
|
|
// {2-0} = Rn
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
|
|
unsigned Rn = getARMRegisterNumbering(MO.getReg());
|
|
unsigned Imm5 = MO1.getImm();
|
|
return ((Imm5 & 0x1f) << 3) | Rn;
|
|
}
|
|
|
|
/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
|
|
}
|
|
|
|
/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
|
|
uint32_t ARMMCCodeEmitter::
|
|
getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// {12-9} = reg
|
|
// {8} = (U)nsigned (add == '1', sub == '0')
|
|
// {7-0} = imm8
|
|
unsigned Reg, Imm8;
|
|
bool isAdd;
|
|
// If The first operand isn't a register, we have a label reference.
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
if (!MO.isReg()) {
|
|
Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
|
|
Imm8 = 0;
|
|
isAdd = false; // 'U' bit is handled as part of the fixup.
|
|
|
|
assert(MO.isExpr() && "Unexpected machine operand type!");
|
|
const MCExpr *Expr = MO.getExpr();
|
|
MCFixupKind Kind;
|
|
if (isThumb2())
|
|
Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
|
|
else
|
|
Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
|
|
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
|
|
|
|
++MCNumCPRelocations;
|
|
} else {
|
|
EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
|
|
isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
|
|
}
|
|
|
|
uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
|
|
// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
|
|
if (isAdd)
|
|
Binary |= (1 << 8);
|
|
Binary |= (Reg << 9);
|
|
return Binary;
|
|
}
|
|
|
|
unsigned ARMMCCodeEmitter::
|
|
getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
|
|
// shifted. The second is either Rs, the amount to shift by, or reg0 in which
|
|
// case the imm contains the amount to shift by.
|
|
//
|
|
// {3-0} = Rm.
|
|
// {4} = 1 if reg shift, 0 if imm shift
|
|
// {6-5} = type
|
|
// If reg shift:
|
|
// {11-8} = Rs
|
|
// {7} = 0
|
|
// else (imm shift)
|
|
// {11-7} = imm
|
|
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
|
|
const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
|
|
ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
|
|
|
|
// Encode Rm.
|
|
unsigned Binary = getARMRegisterNumbering(MO.getReg());
|
|
|
|
// Encode the shift opcode.
|
|
unsigned SBits = 0;
|
|
unsigned Rs = MO1.getReg();
|
|
if (Rs) {
|
|
// Set shift operand (bit[7:4]).
|
|
// LSL - 0001
|
|
// LSR - 0011
|
|
// ASR - 0101
|
|
// ROR - 0111
|
|
switch (SOpc) {
|
|
default: llvm_unreachable("Unknown shift opc!");
|
|
case ARM_AM::lsl: SBits = 0x1; break;
|
|
case ARM_AM::lsr: SBits = 0x3; break;
|
|
case ARM_AM::asr: SBits = 0x5; break;
|
|
case ARM_AM::ror: SBits = 0x7; break;
|
|
}
|
|
}
|
|
|
|
Binary |= SBits << 4;
|
|
|
|
// Encode the shift operation Rs or shift_imm (except rrx).
|
|
// Encode Rs bit[11:8].
|
|
assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
|
|
return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
|
|
}
|
|
|
|
unsigned ARMMCCodeEmitter::
|
|
getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
|
|
// shifted. The second is either Rs, the amount to shift by, or reg0 in which
|
|
// case the imm contains the amount to shift by.
|
|
//
|
|
// {3-0} = Rm.
|
|
// {4} = 1 if reg shift, 0 if imm shift
|
|
// {6-5} = type
|
|
// If reg shift:
|
|
// {11-8} = Rs
|
|
// {7} = 0
|
|
// else (imm shift)
|
|
// {11-7} = imm
|
|
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
|
|
ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
|
|
|
|
// Encode Rm.
|
|
unsigned Binary = getARMRegisterNumbering(MO.getReg());
|
|
|
|
// Encode the shift opcode.
|
|
unsigned SBits = 0;
|
|
|
|
// Set shift operand (bit[6:4]).
|
|
// LSL - 000
|
|
// LSR - 010
|
|
// ASR - 100
|
|
// ROR - 110
|
|
// RRX - 110 and bit[11:8] clear.
|
|
switch (SOpc) {
|
|
default: llvm_unreachable("Unknown shift opc!");
|
|
case ARM_AM::lsl: SBits = 0x0; break;
|
|
case ARM_AM::lsr: SBits = 0x2; break;
|
|
case ARM_AM::asr: SBits = 0x4; break;
|
|
case ARM_AM::ror: SBits = 0x6; break;
|
|
case ARM_AM::rrx:
|
|
Binary |= 0x60;
|
|
return Binary;
|
|
}
|
|
|
|
// Encode shift_imm bit[11:7].
|
|
Binary |= SBits << 4;
|
|
return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
|
|
}
|
|
|
|
|
|
unsigned ARMMCCodeEmitter::
|
|
getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
const MCOperand &MO1 = MI.getOperand(OpNum);
|
|
const MCOperand &MO2 = MI.getOperand(OpNum+1);
|
|
const MCOperand &MO3 = MI.getOperand(OpNum+2);
|
|
|
|
// Encoded as [Rn, Rm, imm].
|
|
// FIXME: Needs fixup support.
|
|
unsigned Value = getARMRegisterNumbering(MO1.getReg());
|
|
Value <<= 4;
|
|
Value |= getARMRegisterNumbering(MO2.getReg());
|
|
Value <<= 2;
|
|
Value |= MO3.getImm();
|
|
|
|
return Value;
|
|
}
|
|
|
|
unsigned ARMMCCodeEmitter::
|
|
getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
const MCOperand &MO1 = MI.getOperand(OpNum);
|
|
const MCOperand &MO2 = MI.getOperand(OpNum+1);
|
|
|
|
// FIXME: Needs fixup support.
|
|
unsigned Value = getARMRegisterNumbering(MO1.getReg());
|
|
|
|
// Even though the immediate is 8 bits long, we need 9 bits in order
|
|
// to represent the (inverse of the) sign bit.
|
|
Value <<= 9;
|
|
int32_t tmp = (int32_t)MO2.getImm();
|
|
if (tmp < 0)
|
|
tmp = abs(tmp);
|
|
else
|
|
Value |= 256; // Set the ADD bit
|
|
Value |= tmp & 255;
|
|
return Value;
|
|
}
|
|
|
|
unsigned ARMMCCodeEmitter::
|
|
getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
const MCOperand &MO1 = MI.getOperand(OpNum);
|
|
|
|
// FIXME: Needs fixup support.
|
|
unsigned Value = 0;
|
|
int32_t tmp = (int32_t)MO1.getImm();
|
|
if (tmp < 0)
|
|
tmp = abs(tmp);
|
|
else
|
|
Value |= 256; // Set the ADD bit
|
|
Value |= tmp & 255;
|
|
return Value;
|
|
}
|
|
|
|
unsigned ARMMCCodeEmitter::
|
|
getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
const MCOperand &MO1 = MI.getOperand(OpNum);
|
|
|
|
// FIXME: Needs fixup support.
|
|
unsigned Value = 0;
|
|
int32_t tmp = (int32_t)MO1.getImm();
|
|
if (tmp < 0)
|
|
tmp = abs(tmp);
|
|
else
|
|
Value |= 4096; // Set the ADD bit
|
|
Value |= tmp & 4095;
|
|
return Value;
|
|
}
|
|
|
|
unsigned ARMMCCodeEmitter::
|
|
getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// Sub-operands are [reg, imm]. The first register is Rm, the reg to be
|
|
// shifted. The second is the amount to shift by.
|
|
//
|
|
// {3-0} = Rm.
|
|
// {4} = 0
|
|
// {6-5} = type
|
|
// {11-7} = imm
|
|
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
|
|
ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
|
|
|
|
// Encode Rm.
|
|
unsigned Binary = getARMRegisterNumbering(MO.getReg());
|
|
|
|
// Encode the shift opcode.
|
|
unsigned SBits = 0;
|
|
// Set shift operand (bit[6:4]).
|
|
// LSL - 000
|
|
// LSR - 010
|
|
// ASR - 100
|
|
// ROR - 110
|
|
switch (SOpc) {
|
|
default: llvm_unreachable("Unknown shift opc!");
|
|
case ARM_AM::lsl: SBits = 0x0; break;
|
|
case ARM_AM::lsr: SBits = 0x2; break;
|
|
case ARM_AM::asr: SBits = 0x4; break;
|
|
case ARM_AM::ror: SBits = 0x6; break;
|
|
}
|
|
|
|
Binary |= SBits << 4;
|
|
if (SOpc == ARM_AM::rrx)
|
|
return Binary;
|
|
|
|
// Encode shift_imm bit[11:7].
|
|
return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
|
|
}
|
|
|
|
unsigned ARMMCCodeEmitter::
|
|
getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
|
|
// msb of the mask.
|
|
const MCOperand &MO = MI.getOperand(Op);
|
|
uint32_t v = ~MO.getImm();
|
|
uint32_t lsb = CountTrailingZeros_32(v);
|
|
uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
|
|
assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
|
|
return lsb | (msb << 5);
|
|
}
|
|
|
|
unsigned ARMMCCodeEmitter::
|
|
getMsbOpValue(const MCInst &MI, unsigned Op,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// MSB - 5 bits.
|
|
uint32_t lsb = MI.getOperand(Op-1).getImm();
|
|
uint32_t width = MI.getOperand(Op).getImm();
|
|
uint32_t msb = lsb+width-1;
|
|
assert (width != 0 && msb < 32 && "Illegal bit width!");
|
|
return msb;
|
|
}
|
|
|
|
namespace llvm {
|
|
// FIXME: TableGen this?
|
|
extern MCRegisterClass ARMMCRegisterClasses[]; // In ARMGenRegisterInfo.inc.
|
|
}
|
|
|
|
unsigned ARMMCCodeEmitter::
|
|
getRegisterListOpValue(const MCInst &MI, unsigned Op,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// VLDM/VSTM:
|
|
// {12-8} = Vd
|
|
// {7-0} = Number of registers
|
|
//
|
|
// LDM/STM:
|
|
// {15-0} = Bitfield of GPRs.
|
|
unsigned Reg = MI.getOperand(Op).getReg();
|
|
bool SPRRegs = llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
|
|
bool DPRRegs = llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
|
|
|
|
unsigned Binary = 0;
|
|
|
|
if (SPRRegs || DPRRegs) {
|
|
// VLDM/VSTM
|
|
unsigned RegNo = getARMRegisterNumbering(Reg);
|
|
unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
|
|
Binary |= (RegNo & 0x1f) << 8;
|
|
if (SPRRegs)
|
|
Binary |= NumRegs;
|
|
else
|
|
Binary |= NumRegs * 2;
|
|
} else {
|
|
for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
|
|
unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
|
|
Binary |= 1 << RegNo;
|
|
}
|
|
}
|
|
|
|
return Binary;
|
|
}
|
|
|
|
/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
|
|
/// with the alignment operand.
|
|
unsigned ARMMCCodeEmitter::
|
|
getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
const MCOperand &Reg = MI.getOperand(Op);
|
|
const MCOperand &Imm = MI.getOperand(Op + 1);
|
|
|
|
unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
|
|
unsigned Align = 0;
|
|
|
|
switch (Imm.getImm()) {
|
|
default: break;
|
|
case 2:
|
|
case 4:
|
|
case 8: Align = 0x01; break;
|
|
case 16: Align = 0x02; break;
|
|
case 32: Align = 0x03; break;
|
|
}
|
|
|
|
return RegNo | (Align << 4);
|
|
}
|
|
|
|
/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
|
|
/// along with the alignment operand for use in VST1 and VLD1 with size 32.
|
|
unsigned ARMMCCodeEmitter::
|
|
getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
const MCOperand &Reg = MI.getOperand(Op);
|
|
const MCOperand &Imm = MI.getOperand(Op + 1);
|
|
|
|
unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
|
|
unsigned Align = 0;
|
|
|
|
switch (Imm.getImm()) {
|
|
default: break;
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
case 16: Align = 0x00; break;
|
|
case 32: Align = 0x03; break;
|
|
}
|
|
|
|
return RegNo | (Align << 4);
|
|
}
|
|
|
|
|
|
/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
|
|
/// alignment operand for use in VLD-dup instructions. This is the same as
|
|
/// getAddrMode6AddressOpValue except for the alignment encoding, which is
|
|
/// different for VLD4-dup.
|
|
unsigned ARMMCCodeEmitter::
|
|
getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
const MCOperand &Reg = MI.getOperand(Op);
|
|
const MCOperand &Imm = MI.getOperand(Op + 1);
|
|
|
|
unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
|
|
unsigned Align = 0;
|
|
|
|
switch (Imm.getImm()) {
|
|
default: break;
|
|
case 2:
|
|
case 4:
|
|
case 8: Align = 0x01; break;
|
|
case 16: Align = 0x03; break;
|
|
}
|
|
|
|
return RegNo | (Align << 4);
|
|
}
|
|
|
|
unsigned ARMMCCodeEmitter::
|
|
getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
const MCOperand &MO = MI.getOperand(Op);
|
|
if (MO.getReg() == 0) return 0x0D;
|
|
return MO.getReg();
|
|
}
|
|
|
|
unsigned ARMMCCodeEmitter::
|
|
getShiftRight8Imm(const MCInst &MI, unsigned Op,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
return 8 - MI.getOperand(Op).getImm();
|
|
}
|
|
|
|
unsigned ARMMCCodeEmitter::
|
|
getShiftRight16Imm(const MCInst &MI, unsigned Op,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
return 16 - MI.getOperand(Op).getImm();
|
|
}
|
|
|
|
unsigned ARMMCCodeEmitter::
|
|
getShiftRight32Imm(const MCInst &MI, unsigned Op,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
return 32 - MI.getOperand(Op).getImm();
|
|
}
|
|
|
|
unsigned ARMMCCodeEmitter::
|
|
getShiftRight64Imm(const MCInst &MI, unsigned Op,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
return 64 - MI.getOperand(Op).getImm();
|
|
}
|
|
|
|
void ARMMCCodeEmitter::
|
|
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// Pseudo instructions don't get encoded.
|
|
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
|
|
uint64_t TSFlags = Desc.TSFlags;
|
|
if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
|
|
return;
|
|
|
|
int Size;
|
|
if (Desc.getSize() == 2 || Desc.getSize() == 4)
|
|
Size = Desc.getSize();
|
|
else
|
|
llvm_unreachable("Unexpected instruction size!");
|
|
|
|
uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
|
|
// Thumb 32-bit wide instructions need to emit the high order halfword
|
|
// first.
|
|
if (isThumb() && Size == 4) {
|
|
EmitConstant(Binary >> 16, 2, OS);
|
|
EmitConstant(Binary & 0xffff, 2, OS);
|
|
} else
|
|
EmitConstant(Binary, Size, OS);
|
|
++MCNumEmitted; // Keep track of the # of mi's emitted.
|
|
}
|
|
|
|
#include "ARMGenMCCodeEmitter.inc"
|